From 81337eb41dca51fcdba7572b0449927732f4f3b5 Mon Sep 17 00:00:00 2001 From: zedarider Date: Thu, 1 Dec 2016 23:57:19 +0000 Subject: adding part 2 and 3 --- part_2/ex9_final/verilog_files/counter_16.v.bak | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100755 part_2/ex9_final/verilog_files/counter_16.v.bak (limited to 'part_2/ex9_final/verilog_files/counter_16.v.bak') diff --git a/part_2/ex9_final/verilog_files/counter_16.v.bak b/part_2/ex9_final/verilog_files/counter_16.v.bak new file mode 100755 index 0000000..c0ec549 --- /dev/null +++ b/part_2/ex9_final/verilog_files/counter_16.v.bak @@ -0,0 +1,21 @@ +`timescale 1ns / 100ps + +module counter_16(clock,enable,reset,count); + + parameter BIT_SZ = 16; + input clock, enable, reset; + output [BIT_SZ-1:0] count; + + reg [BIT_SZ-1:0] count; + + initial count = 0; + + always @ (posedge clock) + begin + if(enable == 1'b1) + count <= count + 1'b1; + if(reset == 1'b1) + count <= 16'b0; + end + +endmodule \ No newline at end of file -- cgit