From 81337eb41dca51fcdba7572b0449927732f4f3b5 Mon Sep 17 00:00:00 2001
From: zedarider <ymherklotz@gmail.com>
Date: Thu, 1 Dec 2016 23:57:19 +0000
Subject: adding part 2 and 3

---
 part_3/ex10/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100755 part_3/ex10/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak

(limited to 'part_3/ex10/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak')

diff --git a/part_3/ex10/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak b/part_3/ex10/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak
new file mode 100755
index 0000000..281cccf
--- /dev/null
+++ b/part_3/ex10/simulation/modelsim/ex10_run_msim_rtl_verilog.do.bak
@@ -0,0 +1,9 @@
+transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+vlib rtl_work
+vmap work rtl_work
+
+vlog -vlog01compat -work work +incdir+C:/New\ folder/ex10/verilog_files {C:/New folder/ex10/verilog_files/spi2dac.v}
+
-- 
cgit