From 81337eb41dca51fcdba7572b0449927732f4f3b5 Mon Sep 17 00:00:00 2001 From: zedarider Date: Thu, 1 Dec 2016 23:57:19 +0000 Subject: adding part 2 and 3 --- part_3/ex11/output_files/ex10.eda.rpt | 96 +++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100755 part_3/ex11/output_files/ex10.eda.rpt (limited to 'part_3/ex11/output_files/ex10.eda.rpt') diff --git a/part_3/ex11/output_files/ex10.eda.rpt b/part_3/ex11/output_files/ex10.eda.rpt new file mode 100755 index 0000000..2346b05 --- /dev/null +++ b/part_3/ex11/output_files/ex10.eda.rpt @@ -0,0 +1,96 @@ +EDA Netlist Writer report for ex10 +Tue Nov 29 11:05:49 2016 +Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2016 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Altera and sold by Altera or its +authorized distributors. Please refer to the applicable +agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Tue Nov 29 11:05:49 2016 ; +; Revision Name ; ex10 ; +; Top-level Entity Name ; ex11 ; +; Family ; Cyclone V ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate functional simulation netlist ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++------------------------------------------------+ +; Simulation Generated Files ; ++------------------------------------------------+ +; Generated Files ; ++------------------------------------------------+ +; C:/New folder/ex11/simulation/modelsim/ex10.vo ; ++------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition + Info: Processing started: Tue Nov 29 11:05:47 2016 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off ex10 -c ex10 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device. +Info (204019): Generated file ex10.vo in folder "C:/New folder/ex11/simulation/modelsim/" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings + Info: Peak virtual memory: 805 megabytes + Info: Processing ended: Tue Nov 29 11:05:49 2016 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:01 + + -- cgit