From 81337eb41dca51fcdba7572b0449927732f4f3b5 Mon Sep 17 00:00:00 2001 From: zedarider Date: Thu, 1 Dec 2016 23:57:19 +0000 Subject: adding part 2 and 3 --- part_3/ex11/verilog_files/tick_5000.v | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100755 part_3/ex11/verilog_files/tick_5000.v (limited to 'part_3/ex11/verilog_files/tick_5000.v') diff --git a/part_3/ex11/verilog_files/tick_5000.v b/part_3/ex11/verilog_files/tick_5000.v new file mode 100755 index 0000000..a048386 --- /dev/null +++ b/part_3/ex11/verilog_files/tick_5000.v @@ -0,0 +1,32 @@ +module tick_5000(CLOCK_IN, CLK_OUT); + + parameter NBIT = 16; + + input CLOCK_IN; + output CLK_OUT; + + reg [NBIT-1:0] count; + + reg CLK_OUT; + + initial + begin + count = 16'd4999; + CLK_OUT = 1'b0; + end + + always @ (posedge CLOCK_IN) + begin + if(count == 16'b0) + begin + CLK_OUT <= 1'b1; + count <= 16'd4999; + end + else + begin + count <= count - 1'b1; + CLK_OUT <= 1'b0; + end + end + +endmodule \ No newline at end of file -- cgit