From 81337eb41dca51fcdba7572b0449927732f4f3b5 Mon Sep 17 00:00:00 2001 From: zedarider Date: Thu, 1 Dec 2016 23:57:19 +0000 Subject: adding part 2 and 3 --- part_3/ex13/verilog_files/counter_10.v | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100755 part_3/ex13/verilog_files/counter_10.v (limited to 'part_3/ex13/verilog_files/counter_10.v') diff --git a/part_3/ex13/verilog_files/counter_10.v b/part_3/ex13/verilog_files/counter_10.v new file mode 100755 index 0000000..72c96fa --- /dev/null +++ b/part_3/ex13/verilog_files/counter_10.v @@ -0,0 +1,18 @@ +`timescale 1ns / 100ps + +module counter_10(clock,enable,count); + + parameter BIT_SZ = 10; + input clock; + input enable; + output [BIT_SZ-1:0] count; + + reg [BIT_SZ-1:0] count; + + initial count = 0; + + always @ (posedge clock) + if(enable == 1'b1) + count <= count + 1'b1; + +endmodule \ No newline at end of file -- cgit