vendor_name = ModelSim
source_file = 1, C:/New folder/ex10/verilog_files/tick_5000.v
source_file = 1, C:/New folder/ex10/verilog_files/spi2dac.v
source_file = 1, C:/New folder/ex10/ex10.v
source_file = 1, C:/New folder/ex10/db/ex10.cbx.xml
design_name = ex10
instance = comp, \DAC_CS~output , DAC_CS~output, ex10, 1
instance = comp, \DAC_SDI~output , DAC_SDI~output, ex10, 1
instance = comp, \DAC_LD~output , DAC_LD~output, ex10, 1
instance = comp, \DAC_SCK~output , DAC_SCK~output, ex10, 1
instance = comp, \CLOCK_50~input , CLOCK_50~input, ex10, 1
instance = comp, \CLOCK_50~inputCLKENA0 , CLOCK_50~inputCLKENA0, ex10, 1
instance = comp, \s|ctr[0] , s|ctr[0], ex10, 1
instance = comp, \s|Add0~1 , s|Add0~1, ex10, 1
instance = comp, \s|ctr[3] , s|ctr[3], ex10, 1
instance = comp, \s|ctr[2] , s|ctr[2], ex10, 1
instance = comp, \s|Add0~0 , s|Add0~0, ex10, 1
instance = comp, \s|ctr[4] , s|ctr[4], ex10, 1
instance = comp, \s|ctr~1 , s|ctr~1, ex10, 1
instance = comp, \s|ctr[0]~DUPLICATE , s|ctr[0]~DUPLICATE, ex10, 1
instance = comp, \s|ctr[1] , s|ctr[1], ex10, 1
instance = comp, \s|ctr~2 , s|ctr~2, ex10, 1
instance = comp, \s|ctr[1]~DUPLICATE , s|ctr[1]~DUPLICATE, ex10, 1
instance = comp, \s|ctr~0 , s|ctr~0, ex10, 1
instance = comp, \s|ctr[2]~DUPLICATE , s|ctr[2]~DUPLICATE, ex10, 1
instance = comp, \s|clk_1MHz~0 , s|clk_1MHz~0, ex10, 1
instance = comp, \s|clk_1MHz , s|clk_1MHz, ex10, 1
instance = comp, \t|Add0~9 , t|Add0~9, ex10, 1
instance = comp, \t|count[0]~1 , t|count[0]~1, ex10, 1
instance = comp, \t|count[0] , t|count[0], ex10, 1
instance = comp, \t|Add0~13 , t|Add0~13, ex10, 1
instance = comp, \t|count[1]~2 , t|count[1]~2, ex10, 1
instance = comp, \t|count[1] , t|count[1], ex10, 1
instance = comp, \t|Add0~17 , t|Add0~17, ex10, 1
instance = comp, \t|count[2]~3 , t|count[2]~3, ex10, 1
instance = comp, \t|count[2] , t|count[2], ex10, 1
instance = comp, \t|Add0~53 , t|Add0~53, ex10, 1
instance = comp, \t|count[3]~DUPLICATE , t|count[3]~DUPLICATE, ex10, 1
instance = comp, \t|Add0~49 , t|Add0~49, ex10, 1
instance = comp, \t|count[4]~DUPLICATE , t|count[4]~DUPLICATE, ex10, 1
instance = comp, \t|Add0~5 , t|Add0~5, ex10, 1
instance = comp, \t|count[5] , t|count[5], ex10, 1
instance = comp, \t|Add0~57 , t|Add0~57, ex10, 1
instance = comp, \t|count[6] , t|count[6], ex10, 1
instance = comp, \t|count[4] , t|count[4], ex10, 1
instance = comp, \t|count[3] , t|count[3], ex10, 1
instance = comp, \t|Add0~21 , t|Add0~21, ex10, 1
instance = comp, \t|count[7]~4 , t|count[7]~4, ex10, 1
instance = comp, \t|count[7]~DUPLICATE , t|count[7]~DUPLICATE, ex10, 1
instance = comp, \t|Add0~25 , t|Add0~25, ex10, 1
instance = comp, \t|count[8]~5 , t|count[8]~5, ex10, 1
instance = comp, \t|count[8] , t|count[8], ex10, 1
instance = comp, \t|Add0~1 , t|Add0~1, ex10, 1
instance = comp, \t|count[9]~0 , t|count[9]~0, ex10, 1
instance = comp, \t|count[9] , t|count[9], ex10, 1
instance = comp, \t|Add0~33 , t|Add0~33, ex10, 1
instance = comp, \t|count[10] , t|count[10], ex10, 1
instance = comp, \t|Add0~61 , t|Add0~61, ex10, 1
instance = comp, \t|count[11] , t|count[11], ex10, 1
instance = comp, \t|Equal0~2 , t|Equal0~2, ex10, 1
instance = comp, \t|Add0~29 , t|Add0~29, ex10, 1
instance = comp, \t|count[12]~6 , t|count[12]~6, ex10, 1
instance = comp, \t|count[12]~DUPLICATE , t|count[12]~DUPLICATE, ex10, 1
instance = comp, \t|Add0~37 , t|Add0~37, ex10, 1
instance = comp, \t|count[13] , t|count[13], ex10, 1
instance = comp, \t|count[12] , t|count[12], ex10, 1
instance = comp, \t|Add0~41 , t|Add0~41, ex10, 1
instance = comp, \t|count[14] , t|count[14], ex10, 1
instance = comp, \t|Add0~45 , t|Add0~45, ex10, 1
instance = comp, \t|count[15] , t|count[15], ex10, 1
instance = comp, \t|Equal0~1 , t|Equal0~1, ex10, 1
instance = comp, \t|count[7] , t|count[7], ex10, 1
instance = comp, \t|count[2]~DUPLICATE , t|count[2]~DUPLICATE, ex10, 1
instance = comp, \t|count[1]~DUPLICATE , t|count[1]~DUPLICATE, ex10, 1
instance = comp, \t|Equal0~0 , t|Equal0~0, ex10, 1
instance = comp, \t|Equal0~3 , t|Equal0~3, ex10, 1
instance = comp, \t|CLK_OUT , t|CLK_OUT, ex10, 1
instance = comp, \s|sr_state.IDLE~0 , s|sr_state.IDLE~0, ex10, 1
instance = comp, \s|sr_state.IDLE , s|sr_state.IDLE, ex10, 1
instance = comp, \s|state[2]~DUPLICATE , s|state[2]~DUPLICATE, ex10, 1
instance = comp, \s|state~2 , s|state~2, ex10, 1
instance = comp, \s|state[2] , s|state[2], ex10, 1
instance = comp, \s|state~3 , s|state~3, ex10, 1
instance = comp, \s|state[3] , s|state[3], ex10, 1
instance = comp, \s|state~0 , s|state~0, ex10, 1
instance = comp, \s|state[4] , s|state[4], ex10, 1
instance = comp, \s|state~1 , s|state~1, ex10, 1
instance = comp, \s|state[1] , s|state[1], ex10, 1
instance = comp, \s|Selector2~0 , s|Selector2~0, ex10, 1
instance = comp, \s|sr_state.WAIT_CSB_HIGH , s|sr_state.WAIT_CSB_HIGH, ex10, 1
instance = comp, \s|sr_state.WAIT_CSB_FALL~0 , s|sr_state.WAIT_CSB_FALL~0, ex10, 1
instance = comp, \s|sr_state.WAIT_CSB_FALL , s|sr_state.WAIT_CSB_FALL, ex10, 1
instance = comp, \s|Selector3~0 , s|Selector3~0, ex10, 1
instance = comp, \s|state[0] , s|state[0], ex10, 1
instance = comp, \s|WideNor0 , s|WideNor0, ex10, 1
instance = comp, \SW[9]~input , SW[9]~input, ex10, 1
instance = comp, \s|shift_reg[11]~feeder , s|shift_reg[11]~feeder, ex10, 1
instance = comp, \SW[8]~input , SW[8]~input, ex10, 1
instance = comp, \s|shift_reg[10]~feeder , s|shift_reg[10]~feeder, ex10, 1
instance = comp, \SW[7]~input , SW[7]~input, ex10, 1
instance = comp, \s|shift_reg[9]~feeder , s|shift_reg[9]~feeder, ex10, 1
instance = comp, \SW[6]~input , SW[6]~input, ex10, 1
instance = comp, \s|shift_reg[8]~feeder , s|shift_reg[8]~feeder, ex10, 1
instance = comp, \SW[5]~input , SW[5]~input, ex10, 1
instance = comp, \s|shift_reg[7]~feeder , s|shift_reg[7]~feeder, ex10, 1
instance = comp, \SW[4]~input , SW[4]~input, ex10, 1
instance = comp, \s|shift_reg[6]~feeder , s|shift_reg[6]~feeder, ex10, 1
instance = comp, \SW[3]~input , SW[3]~input, ex10, 1
instance = comp, \s|shift_reg[5]~feeder , s|shift_reg[5]~feeder, ex10, 1
instance = comp, \SW[2]~input , SW[2]~input, ex10, 1
instance = comp, \s|shift_reg[4]~feeder , s|shift_reg[4]~feeder, ex10, 1
instance = comp, \SW[1]~input , SW[1]~input, ex10, 1
instance = comp, \s|shift_reg[3]~feeder , s|shift_reg[3]~feeder, ex10, 1
instance = comp, \SW[0]~input , SW[0]~input, ex10, 1
instance = comp, \s|shift_reg~4 , s|shift_reg~4, ex10, 1
instance = comp, \s|shift_reg[2] , s|shift_reg[2], ex10, 1
instance = comp, \s|always5~0 , s|always5~0, ex10, 1
instance = comp, \s|shift_reg[3] , s|shift_reg[3], ex10, 1
instance = comp, \s|shift_reg[4] , s|shift_reg[4], ex10, 1
instance = comp, \s|shift_reg[5] , s|shift_reg[5], ex10, 1
instance = comp, \s|shift_reg[6] , s|shift_reg[6], ex10, 1
instance = comp, \s|shift_reg[7] , s|shift_reg[7], ex10, 1
instance = comp, \s|shift_reg[8] , s|shift_reg[8], ex10, 1
instance = comp, \s|shift_reg[9] , s|shift_reg[9], ex10, 1
instance = comp, \s|shift_reg[10] , s|shift_reg[10], ex10, 1
instance = comp, \s|shift_reg[11] , s|shift_reg[11], ex10, 1
instance = comp, \s|shift_reg~3 , s|shift_reg~3, ex10, 1
instance = comp, \s|shift_reg[12] , s|shift_reg[12], ex10, 1
instance = comp, \s|shift_reg~2 , s|shift_reg~2, ex10, 1
instance = comp, \s|shift_reg[13] , s|shift_reg[13], ex10, 1
instance = comp, \s|shift_reg~1 , s|shift_reg~1, ex10, 1
instance = comp, \s|shift_reg[14] , s|shift_reg[14], ex10, 1
instance = comp, \s|shift_reg~0 , s|shift_reg~0, ex10, 1
instance = comp, \s|shift_reg[15] , s|shift_reg[15], ex10, 1
instance = comp, \s|Equal2~0 , s|Equal2~0, ex10, 1
instance = comp, \s|dac_sck , s|dac_sck, ex10, 1
instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, ex10, 1