|ex15 CLOCK_50 => CLOCK_50.IN5 DAC_CS <= spi2dac:dac.port4 DAC_SDI <= spi2dac:dac.port3 DAC_LD <= spi2dac:dac.port6 DAC_SCK <= spi2dac:dac.port5 ADC_SDI <= spi2adc:SPI_ADC.sdata_to_adc ADC_SCK <= spi2adc:SPI_ADC.adc_sck ADC_CS <= spi2adc:SPI_ADC.adc_cs ADC_SDO => ADC_SDO.IN1 PWM_OUT <= pwm:p.port3 HEX0[0] <= hex_to_7seg:h0.port0 HEX0[1] <= hex_to_7seg:h0.port0 HEX0[2] <= hex_to_7seg:h0.port0 HEX0[3] <= hex_to_7seg:h0.port0 HEX0[4] <= hex_to_7seg:h0.port0 HEX0[5] <= hex_to_7seg:h0.port0 HEX0[6] <= hex_to_7seg:h0.port0 HEX1[0] <= hex_to_7seg:h1.port0 HEX1[1] <= hex_to_7seg:h1.port0 HEX1[2] <= hex_to_7seg:h1.port0 HEX1[3] <= hex_to_7seg:h1.port0 HEX1[4] <= hex_to_7seg:h1.port0 HEX1[5] <= hex_to_7seg:h1.port0 HEX1[6] <= hex_to_7seg:h1.port0 HEX2[0] <= hex_to_7seg:h2.port0 HEX2[1] <= hex_to_7seg:h2.port0 HEX2[2] <= hex_to_7seg:h2.port0 HEX2[3] <= hex_to_7seg:h2.port0 HEX2[4] <= hex_to_7seg:h2.port0 HEX2[5] <= hex_to_7seg:h2.port0 HEX2[6] <= hex_to_7seg:h2.port0 HEX3[0] <= hex_to_7seg:h3.port0 HEX3[1] <= hex_to_7seg:h3.port0 HEX3[2] <= hex_to_7seg:h3.port0 HEX3[3] <= hex_to_7seg:h3.port0 HEX3[4] <= hex_to_7seg:h3.port0 HEX3[5] <= hex_to_7seg:h3.port0 HEX3[6] <= hex_to_7seg:h3.port0 HEX4[0] <= hex_to_7seg:h4.port0 HEX4[1] <= hex_to_7seg:h4.port0 HEX4[2] <= hex_to_7seg:h4.port0 HEX4[3] <= hex_to_7seg:h4.port0 HEX4[4] <= hex_to_7seg:h4.port0 HEX4[5] <= hex_to_7seg:h4.port0 HEX4[6] <= hex_to_7seg:h4.port0 |ex15|tick_5000:tick CLOCK_IN => count[0].CLK CLOCK_IN => count[1].CLK CLOCK_IN => count[2].CLK CLOCK_IN => count[3].CLK CLOCK_IN => count[4].CLK CLOCK_IN => count[5].CLK CLOCK_IN => count[6].CLK CLOCK_IN => count[7].CLK CLOCK_IN => count[8].CLK CLOCK_IN => count[9].CLK CLOCK_IN => count[10].CLK CLOCK_IN => count[11].CLK CLOCK_IN => count[12].CLK CLOCK_IN => count[13].CLK CLOCK_IN => count[14].CLK CLOCK_IN => count[15].CLK CLOCK_IN => CLK_OUT~reg0.CLK CLK_OUT <= CLK_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE |ex15|spi2adc:SPI_ADC sysclk => adc_start.CLK sysclk => clk_1MHz.CLK sysclk => ctr[0].CLK sysclk => ctr[1].CLK sysclk => ctr[2].CLK sysclk => ctr[3].CLK sysclk => ctr[4].CLK sysclk => sr_state~1.DATAIN start => Selector1.IN1 start => adc_start.OUTPUTSELECT start => Selector0.IN1 channel => Selector6.IN6 data_from_adc[0] <= data_from_adc[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_from_adc[1] <= data_from_adc[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_from_adc[2] <= data_from_adc[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_from_adc[3] <= data_from_adc[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_from_adc[4] <= data_from_adc[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_from_adc[5] <= data_from_adc[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_from_adc[6] <= data_from_adc[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_from_adc[7] <= data_from_adc[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_from_adc[8] <= data_from_adc[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_from_adc[9] <= data_from_adc[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE data_valid <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE sdata_to_adc <= adc_din.DB_MAX_OUTPUT_PORT_TYPE adc_cs <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE adc_sck <= adc_sck.DB_MAX_OUTPUT_PORT_TYPE sdata_from_adc => shift_reg[0].DATAIN |ex15|add_offset:fin_address keys[0] => Add0.IN10 keys[1] => Add0.IN9 keys[2] => Add0.IN8 keys[3] => Add0.IN7 keys[4] => Add0.IN6 keys[5] => Add0.IN5 keys[6] => Add0.IN4 keys[7] => Add0.IN3 keys[8] => Add0.IN2 keys[9] => Add0.IN1 tick => address[0]~reg0.CLK tick => address[1]~reg0.CLK tick => address[2]~reg0.CLK tick => address[3]~reg0.CLK tick => address[4]~reg0.CLK tick => address[5]~reg0.CLK tick => address[6]~reg0.CLK tick => address[7]~reg0.CLK tick => address[8]~reg0.CLK tick => address[9]~reg0.CLK address[0] <= address[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE address[1] <= address[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE address[2] <= address[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE address[3] <= address[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE address[4] <= address[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE address[5] <= address[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE address[6] <= address[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE address[7] <= address[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE address[8] <= address[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE address[9] <= address[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE |ex15|ROM:rom address[0] => address[0].IN1 address[1] => address[1].IN1 address[2] => address[2].IN1 address[3] => address[3].IN1 address[4] => address[4].IN1 address[5] => address[5].IN1 address[6] => address[6].IN1 address[7] => address[7].IN1 address[8] => address[8].IN1 address[9] => address[9].IN1 clock => clock.IN1 q[0] <= altsyncram:altsyncram_component.q_a q[1] <= altsyncram:altsyncram_component.q_a q[2] <= altsyncram:altsyncram_component.q_a q[3] <= altsyncram:altsyncram_component.q_a q[4] <= altsyncram:altsyncram_component.q_a q[5] <= altsyncram:altsyncram_component.q_a q[6] <= altsyncram:altsyncram_component.q_a q[7] <= altsyncram:altsyncram_component.q_a q[8] <= altsyncram:altsyncram_component.q_a q[9] <= altsyncram:altsyncram_component.q_a |ex15|ROM:rom|altsyncram:altsyncram_component wren_a => ~NO_FANOUT~ rden_a => ~NO_FANOUT~ wren_b => ~NO_FANOUT~ rden_b => ~NO_FANOUT~ data_a[0] => ~NO_FANOUT~ data_a[1] => ~NO_FANOUT~ data_a[2] => ~NO_FANOUT~ data_a[3] => ~NO_FANOUT~ data_a[4] => ~NO_FANOUT~ data_a[5] => ~NO_FANOUT~ data_a[6] => ~NO_FANOUT~ data_a[7] => ~NO_FANOUT~ data_a[8] => ~NO_FANOUT~ data_a[9] => ~NO_FANOUT~ data_b[0] => ~NO_FANOUT~ address_a[0] => altsyncram_6ng1:auto_generated.address_a[0] address_a[1] => altsyncram_6ng1:auto_generated.address_a[1] address_a[2] => altsyncram_6ng1:auto_generated.address_a[2] address_a[3] => altsyncram_6ng1:auto_generated.address_a[3] address_a[4] => altsyncram_6ng1:auto_generated.address_a[4] address_a[5] => altsyncram_6ng1:auto_generated.address_a[5] address_a[6] => altsyncram_6ng1:auto_generated.address_a[6] address_a[7] => altsyncram_6ng1:auto_generated.address_a[7] address_a[8] => altsyncram_6ng1:auto_generated.address_a[8] address_a[9] => altsyncram_6ng1:auto_generated.address_a[9] address_b[0] => ~NO_FANOUT~ addressstall_a => ~NO_FANOUT~ addressstall_b => ~NO_FANOUT~ clock0 => altsyncram_6ng1:auto_generated.clock0 clock1 => ~NO_FANOUT~ clocken0 => ~NO_FANOUT~ clocken1 => ~NO_FANOUT~ clocken2 => ~NO_FANOUT~ clocken3 => ~NO_FANOUT~ aclr0 => ~NO_FANOUT~ aclr1 => ~NO_FANOUT~ byteena_a[0] => ~NO_FANOUT~ byteena_b[0] => ~NO_FANOUT~ q_a[0] <= altsyncram_6ng1:auto_generated.q_a[0] q_a[1] <= altsyncram_6ng1:auto_generated.q_a[1] q_a[2] <= altsyncram_6ng1:auto_generated.q_a[2] q_a[3] <= altsyncram_6ng1:auto_generated.q_a[3] q_a[4] <= altsyncram_6ng1:auto_generated.q_a[4] q_a[5] <= altsyncram_6ng1:auto_generated.q_a[5] q_a[6] <= altsyncram_6ng1:auto_generated.q_a[6] q_a[7] <= altsyncram_6ng1:auto_generated.q_a[7] q_a[8] <= altsyncram_6ng1:auto_generated.q_a[8] q_a[9] <= altsyncram_6ng1:auto_generated.q_a[9] q_b[0] <= eccstatus[0] <= eccstatus[1] <= eccstatus[2] <= |ex15|ROM:rom|altsyncram:altsyncram_component|altsyncram_6ng1:auto_generated address_a[0] => ram_block1a0.PORTAADDR address_a[0] => ram_block1a1.PORTAADDR address_a[0] => ram_block1a2.PORTAADDR address_a[0] => ram_block1a3.PORTAADDR address_a[0] => ram_block1a4.PORTAADDR address_a[0] => ram_block1a5.PORTAADDR address_a[0] => ram_block1a6.PORTAADDR address_a[0] => ram_block1a7.PORTAADDR address_a[0] => ram_block1a8.PORTAADDR address_a[0] => ram_block1a9.PORTAADDR address_a[1] => ram_block1a0.PORTAADDR1 address_a[1] => ram_block1a1.PORTAADDR1 address_a[1] => ram_block1a2.PORTAADDR1 address_a[1] => ram_block1a3.PORTAADDR1 address_a[1] => ram_block1a4.PORTAADDR1 address_a[1] => ram_block1a5.PORTAADDR1 address_a[1] => ram_block1a6.PORTAADDR1 address_a[1] => ram_block1a7.PORTAADDR1 address_a[1] => ram_block1a8.PORTAADDR1 address_a[1] => ram_block1a9.PORTAADDR1 address_a[2] => ram_block1a0.PORTAADDR2 address_a[2] => ram_block1a1.PORTAADDR2 address_a[2] => ram_block1a2.PORTAADDR2 address_a[2] => ram_block1a3.PORTAADDR2 address_a[2] => ram_block1a4.PORTAADDR2 address_a[2] => ram_block1a5.PORTAADDR2 address_a[2] => ram_block1a6.PORTAADDR2 address_a[2] => ram_block1a7.PORTAADDR2 address_a[2] => ram_block1a8.PORTAADDR2 address_a[2] => ram_block1a9.PORTAADDR2 address_a[3] => ram_block1a0.PORTAADDR3 address_a[3] => ram_block1a1.PORTAADDR3 address_a[3] => ram_block1a2.PORTAADDR3 address_a[3] => ram_block1a3.PORTAADDR3 address_a[3] => ram_block1a4.PORTAADDR3 address_a[3] => ram_block1a5.PORTAADDR3 address_a[3] => ram_block1a6.PORTAADDR3 address_a[3] => ram_block1a7.PORTAADDR3 address_a[3] => ram_block1a8.PORTAADDR3 address_a[3] => ram_block1a9.PORTAADDR3 address_a[4] => ram_block1a0.PORTAADDR4 address_a[4] => ram_block1a1.PORTAADDR4 address_a[4] => ram_block1a2.PORTAADDR4 address_a[4] => ram_block1a3.PORTAADDR4 address_a[4] => ram_block1a4.PORTAADDR4 address_a[4] => ram_block1a5.PORTAADDR4 address_a[4] => ram_block1a6.PORTAADDR4 address_a[4] => ram_block1a7.PORTAADDR4 address_a[4] => ram_block1a8.PORTAADDR4 address_a[4] => ram_block1a9.PORTAADDR4 address_a[5] => ram_block1a0.PORTAADDR5 address_a[5] => ram_block1a1.PORTAADDR5 address_a[5] => ram_block1a2.PORTAADDR5 address_a[5] => ram_block1a3.PORTAADDR5 address_a[5] => ram_block1a4.PORTAADDR5 address_a[5] => ram_block1a5.PORTAADDR5 address_a[5] => ram_block1a6.PORTAADDR5 address_a[5] => ram_block1a7.PORTAADDR5 address_a[5] => ram_block1a8.PORTAADDR5 address_a[5] => ram_block1a9.PORTAADDR5 address_a[6] => ram_block1a0.PORTAADDR6 address_a[6] => ram_block1a1.PORTAADDR6 address_a[6] => ram_block1a2.PORTAADDR6 address_a[6] => ram_block1a3.PORTAADDR6 address_a[6] => ram_block1a4.PORTAADDR6 address_a[6] => ram_block1a5.PORTAADDR6 address_a[6] => ram_block1a6.PORTAADDR6 address_a[6] => ram_block1a7.PORTAADDR6 address_a[6] => ram_block1a8.PORTAADDR6 address_a[6] => ram_block1a9.PORTAADDR6 address_a[7] => ram_block1a0.PORTAADDR7 address_a[7] => ram_block1a1.PORTAADDR7 address_a[7] => ram_block1a2.PORTAADDR7 address_a[7] => ram_block1a3.PORTAADDR7 address_a[7] => ram_block1a4.PORTAADDR7 address_a[7] => ram_block1a5.PORTAADDR7 address_a[7] => ram_block1a6.PORTAADDR7 address_a[7] => ram_block1a7.PORTAADDR7 address_a[7] => ram_block1a8.PORTAADDR7 address_a[7] => ram_block1a9.PORTAADDR7 address_a[8] => ram_block1a0.PORTAADDR8 address_a[8] => ram_block1a1.PORTAADDR8 address_a[8] => ram_block1a2.PORTAADDR8 address_a[8] => ram_block1a3.PORTAADDR8 address_a[8] => ram_block1a4.PORTAADDR8 address_a[8] => ram_block1a5.PORTAADDR8 address_a[8] => ram_block1a6.PORTAADDR8 address_a[8] => ram_block1a7.PORTAADDR8 address_a[8] => ram_block1a8.PORTAADDR8 address_a[8] => ram_block1a9.PORTAADDR8 address_a[9] => ram_block1a0.PORTAADDR9 address_a[9] => ram_block1a1.PORTAADDR9 address_a[9] => ram_block1a2.PORTAADDR9 address_a[9] => ram_block1a3.PORTAADDR9 address_a[9] => ram_block1a4.PORTAADDR9 address_a[9] => ram_block1a5.PORTAADDR9 address_a[9] => ram_block1a6.PORTAADDR9 address_a[9] => ram_block1a7.PORTAADDR9 address_a[9] => ram_block1a8.PORTAADDR9 address_a[9] => ram_block1a9.PORTAADDR9 clock0 => ram_block1a0.CLK0 clock0 => ram_block1a1.CLK0 clock0 => ram_block1a2.CLK0 clock0 => ram_block1a3.CLK0 clock0 => ram_block1a4.CLK0 clock0 => ram_block1a5.CLK0 clock0 => ram_block1a6.CLK0 clock0 => ram_block1a7.CLK0 clock0 => ram_block1a8.CLK0 clock0 => ram_block1a9.CLK0 q_a[0] <= ram_block1a0.PORTADATAOUT q_a[1] <= ram_block1a1.PORTADATAOUT q_a[2] <= ram_block1a2.PORTADATAOUT q_a[3] <= ram_block1a3.PORTADATAOUT q_a[4] <= ram_block1a4.PORTADATAOUT q_a[5] <= ram_block1a5.PORTADATAOUT q_a[6] <= ram_block1a6.PORTADATAOUT q_a[7] <= ram_block1a7.PORTADATAOUT q_a[8] <= ram_block1a8.PORTADATAOUT q_a[9] <= ram_block1a9.PORTADATAOUT |ex15|spi2dac:dac sysclk => clk_1MHz.CLK sysclk => ctr[0].CLK sysclk => ctr[1].CLK sysclk => ctr[2].CLK sysclk => ctr[3].CLK sysclk => ctr[4].CLK sysclk => sr_state~4.DATAIN data_in[0] => shift_reg.DATAB data_in[1] => shift_reg.DATAB data_in[2] => shift_reg.DATAB data_in[3] => shift_reg.DATAB data_in[4] => shift_reg.DATAB data_in[5] => shift_reg.DATAB data_in[6] => shift_reg.DATAB data_in[7] => shift_reg.DATAB data_in[8] => shift_reg.DATAB data_in[9] => shift_reg.DATAB load => sr_state.OUTPUTSELECT load => sr_state.OUTPUTSELECT load => sr_state.OUTPUTSELECT dac_sdi <= shift_reg[15].DB_MAX_OUTPUT_PORT_TYPE dac_cs <= WideNor0.DB_MAX_OUTPUT_PORT_TYPE dac_sck <= dac_sck.DB_MAX_OUTPUT_PORT_TYPE dac_ld <= Equal2.DB_MAX_OUTPUT_PORT_TYPE |ex15|pwm:p clk => pwm_out~reg0.CLK clk => count[0].CLK clk => count[1].CLK clk => count[2].CLK clk => count[3].CLK clk => count[4].CLK clk => count[5].CLK clk => count[6].CLK clk => count[7].CLK clk => count[8].CLK clk => count[9].CLK clk => d[0].CLK clk => d[1].CLK clk => d[2].CLK clk => d[3].CLK clk => d[4].CLK clk => d[5].CLK clk => d[6].CLK clk => d[7].CLK clk => d[8].CLK clk => d[9].CLK data_in[0] => d[0].DATAIN data_in[1] => d[1].DATAIN data_in[2] => d[2].DATAIN data_in[3] => d[3].DATAIN data_in[4] => d[4].DATAIN data_in[5] => d[5].DATAIN data_in[6] => d[6].DATAIN data_in[7] => d[7].DATAIN data_in[8] => d[8].DATAIN data_in[9] => d[9].DATAIN load => d[0].ENA load => d[1].ENA load => d[2].ENA load => d[3].ENA load => d[4].ENA load => d[5].ENA load => d[6].ENA load => d[7].ENA load => d[8].ENA load => d[9].ENA pwm_out <= pwm_out~reg0.DB_MAX_OUTPUT_PORT_TYPE |ex15|const_mult:mult dataa[0] => dataa[0].IN1 dataa[1] => dataa[1].IN1 dataa[2] => dataa[2].IN1 dataa[3] => dataa[3].IN1 dataa[4] => dataa[4].IN1 dataa[5] => dataa[5].IN1 dataa[6] => dataa[6].IN1 dataa[7] => dataa[7].IN1 dataa[8] => dataa[8].IN1 dataa[9] => dataa[9].IN1 result[0] <= lpm_mult:lpm_mult_component.result result[1] <= lpm_mult:lpm_mult_component.result result[2] <= lpm_mult:lpm_mult_component.result result[3] <= lpm_mult:lpm_mult_component.result result[4] <= lpm_mult:lpm_mult_component.result result[5] <= lpm_mult:lpm_mult_component.result result[6] <= lpm_mult:lpm_mult_component.result result[7] <= lpm_mult:lpm_mult_component.result result[8] <= lpm_mult:lpm_mult_component.result result[9] <= lpm_mult:lpm_mult_component.result result[10] <= lpm_mult:lpm_mult_component.result result[11] <= lpm_mult:lpm_mult_component.result result[12] <= lpm_mult:lpm_mult_component.result result[13] <= lpm_mult:lpm_mult_component.result result[14] <= lpm_mult:lpm_mult_component.result result[15] <= lpm_mult:lpm_mult_component.result result[16] <= lpm_mult:lpm_mult_component.result result[17] <= lpm_mult:lpm_mult_component.result result[18] <= lpm_mult:lpm_mult_component.result result[19] <= lpm_mult:lpm_mult_component.result result[20] <= lpm_mult:lpm_mult_component.result result[21] <= lpm_mult:lpm_mult_component.result result[22] <= lpm_mult:lpm_mult_component.result result[23] <= lpm_mult:lpm_mult_component.result |ex15|const_mult:mult|lpm_mult:lpm_mult_component dataa[0] => multcore:mult_core.dataa[0] dataa[1] => multcore:mult_core.dataa[1] dataa[2] => multcore:mult_core.dataa[2] dataa[3] => multcore:mult_core.dataa[3] dataa[4] => multcore:mult_core.dataa[4] dataa[5] => multcore:mult_core.dataa[5] dataa[6] => multcore:mult_core.dataa[6] dataa[7] => multcore:mult_core.dataa[7] dataa[8] => multcore:mult_core.dataa[8] dataa[9] => multcore:mult_core.dataa[9] datab[0] => multcore:mult_core.datab[0] datab[1] => multcore:mult_core.datab[1] datab[2] => multcore:mult_core.datab[2] datab[3] => multcore:mult_core.datab[3] datab[4] => multcore:mult_core.datab[4] datab[5] => multcore:mult_core.datab[5] datab[6] => multcore:mult_core.datab[6] datab[7] => multcore:mult_core.datab[7] datab[8] => multcore:mult_core.datab[8] datab[9] => multcore:mult_core.datab[9] datab[10] => multcore:mult_core.datab[10] datab[11] => multcore:mult_core.datab[11] datab[12] => multcore:mult_core.datab[12] datab[13] => multcore:mult_core.datab[13] sum[0] => ~NO_FANOUT~ aclr => ~NO_FANOUT~ sclr => ~NO_FANOUT~ clock => ~NO_FANOUT~ clken => ~NO_FANOUT~ result[0] <= altshift:external_latency_ffs.result[0] result[1] <= altshift:external_latency_ffs.result[1] result[2] <= altshift:external_latency_ffs.result[2] result[3] <= altshift:external_latency_ffs.result[3] result[4] <= altshift:external_latency_ffs.result[4] result[5] <= altshift:external_latency_ffs.result[5] result[6] <= altshift:external_latency_ffs.result[6] result[7] <= altshift:external_latency_ffs.result[7] result[8] <= altshift:external_latency_ffs.result[8] result[9] <= altshift:external_latency_ffs.result[9] result[10] <= altshift:external_latency_ffs.result[10] result[11] <= altshift:external_latency_ffs.result[11] result[12] <= altshift:external_latency_ffs.result[12] result[13] <= altshift:external_latency_ffs.result[13] result[14] <= altshift:external_latency_ffs.result[14] result[15] <= altshift:external_latency_ffs.result[15] result[16] <= altshift:external_latency_ffs.result[16] result[17] <= altshift:external_latency_ffs.result[17] result[18] <= altshift:external_latency_ffs.result[18] result[19] <= altshift:external_latency_ffs.result[19] result[20] <= altshift:external_latency_ffs.result[20] result[21] <= altshift:external_latency_ffs.result[21] result[22] <= altshift:external_latency_ffs.result[22] result[23] <= altshift:external_latency_ffs.result[23] |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core dataa[0] => _.IN0 dataa[0] => _.IN3 dataa[0] => _.IN0 dataa[0] => _.IN3 dataa[0] => _.IN0 dataa[0] => _.IN3 dataa[0] => _.IN0 dataa[0] => _.IN3 dataa[0] => _.IN0 dataa[0] => _.IN3 dataa[0] => _.IN0 dataa[0] => _.IN3 dataa[0] => _.IN0 dataa[0] => _.IN3 dataa[0] => _.IN0 dataa[0] => _.IN3 dataa[1] => _.IN0 dataa[1] => _.IN0 dataa[1] => _.IN2 dataa[1] => _.IN2 dataa[1] => _.IN0 dataa[1] => _.IN0 dataa[1] => _.IN2 dataa[1] => _.IN2 dataa[1] => _.IN0 dataa[1] => _.IN0 dataa[1] => _.IN2 dataa[1] => _.IN2 dataa[1] => _.IN0 dataa[1] => _.IN0 dataa[1] => _.IN2 dataa[1] => _.IN2 dataa[2] => _.IN0 dataa[2] => _.IN0 dataa[2] => _.IN0 dataa[2] => _.IN0 dataa[2] => _.IN1 dataa[2] => _.IN1 dataa[2] => _.IN1 dataa[2] => _.IN1 dataa[2] => _.IN0 dataa[2] => _.IN0 dataa[2] => _.IN0 dataa[2] => _.IN0 dataa[2] => _.IN1 dataa[2] => _.IN1 dataa[2] => _.IN1 dataa[2] => _.IN1 dataa[3] => _.IN0 dataa[3] => _.IN0 dataa[3] => _.IN0 dataa[3] => _.IN0 dataa[3] => _.IN0 dataa[3] => _.IN0 dataa[3] => _.IN0 dataa[3] => _.IN0 dataa[3] => _.IN0 dataa[3] => _.IN0 dataa[3] => _.IN0 dataa[3] => _.IN0 dataa[3] => _.IN0 dataa[3] => _.IN0 dataa[3] => _.IN0 dataa[3] => _.IN0 dataa[4] => _.IN0 dataa[4] => _.IN3 dataa[4] => _.IN0 dataa[4] => _.IN3 dataa[4] => _.IN0 dataa[4] => _.IN3 dataa[4] => _.IN0 dataa[4] => _.IN3 dataa[4] => _.IN0 dataa[4] => _.IN3 dataa[4] => _.IN0 dataa[4] => _.IN3 dataa[4] => _.IN0 dataa[4] => _.IN3 dataa[4] => _.IN0 dataa[4] => _.IN3 dataa[5] => _.IN0 dataa[5] => _.IN0 dataa[5] => _.IN2 dataa[5] => _.IN2 dataa[5] => _.IN0 dataa[5] => _.IN0 dataa[5] => _.IN2 dataa[5] => _.IN2 dataa[5] => _.IN0 dataa[5] => _.IN0 dataa[5] => _.IN2 dataa[5] => _.IN2 dataa[5] => _.IN0 dataa[5] => _.IN0 dataa[5] => _.IN2 dataa[5] => _.IN2 dataa[6] => _.IN0 dataa[6] => _.IN0 dataa[6] => _.IN0 dataa[6] => _.IN0 dataa[6] => _.IN1 dataa[6] => _.IN1 dataa[6] => _.IN1 dataa[6] => _.IN1 dataa[6] => _.IN0 dataa[6] => _.IN0 dataa[6] => _.IN0 dataa[6] => _.IN0 dataa[6] => _.IN1 dataa[6] => _.IN1 dataa[6] => _.IN1 dataa[6] => _.IN1 dataa[7] => _.IN0 dataa[7] => _.IN0 dataa[7] => _.IN0 dataa[7] => _.IN0 dataa[7] => _.IN0 dataa[7] => _.IN0 dataa[7] => _.IN0 dataa[7] => _.IN0 dataa[7] => _.IN0 dataa[7] => _.IN0 dataa[7] => _.IN0 dataa[7] => _.IN0 dataa[7] => _.IN0 dataa[7] => _.IN0 dataa[7] => _.IN0 dataa[7] => _.IN0 dataa[8] => _.IN0 dataa[8] => _.IN3 dataa[8] => _.IN0 dataa[8] => _.IN3 dataa[8] => _.IN0 dataa[8] => _.IN3 dataa[8] => _.IN0 dataa[8] => _.IN3 dataa[8] => _.IN0 dataa[8] => _.IN3 dataa[8] => _.IN0 dataa[8] => _.IN3 dataa[8] => _.IN0 dataa[8] => _.IN3 dataa[8] => _.IN0 dataa[8] => _.IN3 dataa[9] => ina_reg_clkd[1].IN0 datab[0] => op_1.IN34 datab[0] => op_2.IN35 datab[0] => op_4.IN35 datab[0] => op_5.IN35 datab[0] => op_6.IN35 datab[0] => op_7.IN35 datab[0] => op_8.IN35 datab[0] => op_9.IN35 datab[0] => op_10.IN35 datab[0] => op_11.IN35 datab[0] => romout[0][0].IN1 datab[0] => romout[1][0].IN1 datab[0] => op_1.IN33 datab[0] => op_3.IN33 datab[0] => romout[0][1].IN1 datab[0] => romout[1][1].IN1 datab[0] => op_2.IN30 datab[0] => op_3.IN30 datab[0] => romout[0][2].IN1 datab[0] => romout[1][2].IN1 datab[0] => op_5.IN28 datab[0] => romout[0][3].IN1 datab[0] => romout[1][3].IN1 datab[0] => romout[2][0].IN1 datab[0] => romout[2][1].IN1 datab[0] => romout[2][2].IN1 datab[0] => romout[2][3].IN1 datab[1] => op_1.IN32 datab[1] => op_2.IN33 datab[1] => op_4.IN33 datab[1] => op_5.IN33 datab[1] => op_6.IN33 datab[1] => op_7.IN33 datab[1] => op_8.IN33 datab[1] => op_9.IN33 datab[1] => op_10.IN33 datab[1] => op_11.IN33 datab[1] => romout[0][1].IN1 datab[1] => romout[1][1].IN1 datab[1] => op_1.IN31 datab[1] => op_3.IN31 datab[1] => romout[0][2].IN1 datab[1] => romout[1][2].IN1 datab[1] => op_2.IN28 datab[1] => op_3.IN28 datab[1] => romout[0][3].IN1 datab[1] => romout[1][3].IN1 datab[1] => op_5.IN26 datab[1] => romout[0][4].IN1 datab[1] => romout[1][4].IN1 datab[1] => romout[2][1].IN1 datab[1] => romout[2][2].IN1 datab[1] => romout[2][3].IN1 datab[1] => romout[2][4].IN1 datab[2] => op_1.IN30 datab[2] => op_2.IN31 datab[2] => op_4.IN31 datab[2] => op_5.IN31 datab[2] => op_6.IN31 datab[2] => op_7.IN31 datab[2] => op_8.IN31 datab[2] => op_9.IN31 datab[2] => op_10.IN31 datab[2] => op_11.IN31 datab[2] => romout[0][2].IN1 datab[2] => romout[1][2].IN1 datab[2] => op_1.IN29 datab[2] => op_3.IN29 datab[2] => romout[0][3].IN1 datab[2] => romout[1][3].IN1 datab[2] => op_2.IN26 datab[2] => op_3.IN26 datab[2] => romout[0][4].IN1 datab[2] => romout[1][4].IN1 datab[2] => op_5.IN24 datab[2] => romout[0][5].IN1 datab[2] => romout[1][5].IN1 datab[2] => romout[2][2].IN1 datab[2] => romout[2][3].IN1 datab[2] => romout[2][4].IN1 datab[2] => romout[2][5].IN1 datab[3] => op_1.IN28 datab[3] => op_2.IN29 datab[3] => op_4.IN29 datab[3] => op_5.IN29 datab[3] => op_6.IN29 datab[3] => op_7.IN29 datab[3] => op_8.IN29 datab[3] => op_9.IN29 datab[3] => op_10.IN29 datab[3] => op_11.IN29 datab[3] => romout[0][3].IN1 datab[3] => romout[1][3].IN1 datab[3] => op_1.IN27 datab[3] => op_3.IN27 datab[3] => romout[0][4].IN1 datab[3] => romout[1][4].IN1 datab[3] => op_2.IN24 datab[3] => op_3.IN24 datab[3] => romout[0][5].IN1 datab[3] => romout[1][5].IN1 datab[3] => op_5.IN22 datab[3] => romout[0][6].IN1 datab[3] => romout[1][6].IN1 datab[3] => romout[2][3].IN1 datab[3] => romout[2][4].IN1 datab[3] => romout[2][5].IN1 datab[3] => romout[2][6].IN1 datab[4] => op_1.IN26 datab[4] => op_2.IN27 datab[4] => op_4.IN27 datab[4] => op_5.IN27 datab[4] => op_6.IN27 datab[4] => op_7.IN27 datab[4] => op_8.IN27 datab[4] => op_9.IN27 datab[4] => op_10.IN27 datab[4] => op_11.IN27 datab[4] => romout[0][4].IN1 datab[4] => romout[1][4].IN1 datab[4] => op_1.IN25 datab[4] => op_3.IN25 datab[4] => romout[0][5].IN1 datab[4] => romout[1][5].IN1 datab[4] => op_2.IN22 datab[4] => op_3.IN22 datab[4] => romout[0][6].IN1 datab[4] => romout[1][6].IN1 datab[4] => op_5.IN20 datab[4] => romout[0][7].IN1 datab[4] => romout[1][7].IN1 datab[4] => romout[2][4].IN1 datab[4] => romout[2][5].IN1 datab[4] => romout[2][6].IN1 datab[4] => romout[2][7].IN1 datab[5] => op_1.IN24 datab[5] => op_2.IN25 datab[5] => op_4.IN25 datab[5] => op_5.IN25 datab[5] => op_6.IN25 datab[5] => op_7.IN25 datab[5] => op_8.IN25 datab[5] => op_9.IN25 datab[5] => op_10.IN25 datab[5] => op_11.IN25 datab[5] => romout[0][5].IN1 datab[5] => romout[1][5].IN1 datab[5] => op_1.IN23 datab[5] => op_3.IN23 datab[5] => romout[0][6].IN1 datab[5] => romout[1][6].IN1 datab[5] => op_2.IN20 datab[5] => op_3.IN20 datab[5] => romout[0][7].IN1 datab[5] => romout[1][7].IN1 datab[5] => op_5.IN18 datab[5] => romout[0][8].IN1 datab[5] => romout[1][8].IN1 datab[5] => romout[2][5].IN1 datab[5] => romout[2][6].IN1 datab[5] => romout[2][7].IN1 datab[5] => romout[2][8].IN1 datab[6] => op_1.IN22 datab[6] => op_2.IN23 datab[6] => op_4.IN23 datab[6] => op_5.IN23 datab[6] => op_6.IN23 datab[6] => op_7.IN23 datab[6] => op_8.IN23 datab[6] => op_9.IN23 datab[6] => op_10.IN23 datab[6] => op_11.IN23 datab[6] => romout[0][6].IN1 datab[6] => romout[1][6].IN1 datab[6] => op_1.IN21 datab[6] => op_3.IN21 datab[6] => romout[0][7].IN1 datab[6] => romout[1][7].IN1 datab[6] => op_2.IN18 datab[6] => op_3.IN18 datab[6] => romout[0][8].IN1 datab[6] => romout[1][8].IN1 datab[6] => op_5.IN16 datab[6] => romout[0][9].IN1 datab[6] => romout[1][9].IN1 datab[6] => romout[2][6].IN1 datab[6] => romout[2][7].IN1 datab[6] => romout[2][8].IN1 datab[6] => romout[2][9].IN1 datab[7] => op_1.IN20 datab[7] => op_2.IN21 datab[7] => op_4.IN21 datab[7] => op_5.IN21 datab[7] => op_6.IN21 datab[7] => op_7.IN21 datab[7] => op_8.IN21 datab[7] => op_9.IN21 datab[7] => op_10.IN21 datab[7] => op_11.IN21 datab[7] => romout[0][7].IN1 datab[7] => romout[1][7].IN1 datab[7] => op_1.IN19 datab[7] => op_3.IN19 datab[7] => romout[0][8].IN1 datab[7] => romout[1][8].IN1 datab[7] => op_2.IN16 datab[7] => op_3.IN16 datab[7] => romout[0][9].IN1 datab[7] => romout[1][9].IN1 datab[7] => op_5.IN14 datab[7] => romout[0][10].IN1 datab[7] => romout[1][10].IN1 datab[7] => romout[2][7].IN1 datab[7] => romout[2][8].IN1 datab[7] => romout[2][9].IN1 datab[7] => romout[2][10].IN1 datab[8] => op_1.IN18 datab[8] => op_2.IN19 datab[8] => op_4.IN19 datab[8] => op_5.IN19 datab[8] => op_6.IN19 datab[8] => op_7.IN19 datab[8] => op_8.IN19 datab[8] => op_9.IN19 datab[8] => op_10.IN19 datab[8] => op_11.IN19 datab[8] => romout[0][8].IN1 datab[8] => romout[1][8].IN1 datab[8] => op_1.IN17 datab[8] => op_3.IN17 datab[8] => romout[0][9].IN1 datab[8] => romout[1][9].IN1 datab[8] => op_2.IN14 datab[8] => op_3.IN14 datab[8] => romout[0][10].IN1 datab[8] => romout[1][10].IN1 datab[8] => op_5.IN12 datab[8] => romout[0][11].IN1 datab[8] => romout[1][11].IN1 datab[8] => romout[2][8].IN1 datab[8] => romout[2][9].IN1 datab[8] => romout[2][10].IN1 datab[8] => romout[2][11].IN1 datab[9] => op_1.IN16 datab[9] => op_2.IN17 datab[9] => op_4.IN17 datab[9] => op_5.IN17 datab[9] => op_6.IN17 datab[9] => op_7.IN17 datab[9] => op_8.IN17 datab[9] => op_9.IN17 datab[9] => op_10.IN17 datab[9] => op_11.IN17 datab[9] => romout[0][9].IN1 datab[9] => romout[1][9].IN1 datab[9] => op_1.IN15 datab[9] => op_3.IN15 datab[9] => romout[0][10].IN1 datab[9] => romout[1][10].IN1 datab[9] => op_2.IN12 datab[9] => op_3.IN12 datab[9] => romout[0][11].IN1 datab[9] => romout[1][11].IN1 datab[9] => op_5.IN10 datab[9] => romout[0][12].IN1 datab[9] => romout[1][12].IN1 datab[9] => romout[2][9].IN1 datab[9] => romout[2][10].IN1 datab[9] => romout[2][11].IN1 datab[9] => romout[2][12].IN1 datab[10] => op_1.IN14 datab[10] => op_2.IN15 datab[10] => op_4.IN15 datab[10] => op_5.IN15 datab[10] => op_6.IN15 datab[10] => op_7.IN15 datab[10] => op_8.IN15 datab[10] => op_9.IN15 datab[10] => op_10.IN15 datab[10] => op_11.IN15 datab[10] => romout[0][10].IN1 datab[10] => romout[1][10].IN1 datab[10] => op_1.IN13 datab[10] => op_3.IN13 datab[10] => romout[0][11].IN1 datab[10] => romout[1][11].IN1 datab[10] => op_2.IN10 datab[10] => op_3.IN10 datab[10] => romout[0][12].IN1 datab[10] => romout[1][12].IN1 datab[10] => op_5.IN8 datab[10] => romout[0][13].IN1 datab[10] => romout[1][13].IN1 datab[10] => romout[2][10].IN1 datab[10] => romout[2][11].IN1 datab[10] => romout[2][12].IN1 datab[10] => romout[2][13].IN1 datab[11] => op_1.IN12 datab[11] => op_2.IN13 datab[11] => op_4.IN13 datab[11] => op_5.IN13 datab[11] => op_6.IN13 datab[11] => op_7.IN13 datab[11] => op_8.IN13 datab[11] => op_9.IN13 datab[11] => op_10.IN13 datab[11] => op_11.IN13 datab[11] => romout[0][11].IN1 datab[11] => romout[1][11].IN1 datab[11] => op_1.IN11 datab[11] => op_3.IN11 datab[11] => romout[0][12].IN1 datab[11] => romout[1][12].IN1 datab[11] => op_2.IN8 datab[11] => op_3.IN8 datab[11] => romout[0][13].IN1 datab[11] => romout[1][13].IN1 datab[11] => op_5.IN6 datab[11] => romout[0][14].IN1 datab[11] => romout[1][14].IN1 datab[11] => romout[2][11].IN1 datab[11] => romout[2][12].IN1 datab[11] => romout[2][13].IN1 datab[11] => romout[2][14].IN1 datab[12] => op_1.IN10 datab[12] => op_2.IN11 datab[12] => op_4.IN11 datab[12] => op_5.IN11 datab[12] => op_6.IN11 datab[12] => op_7.IN11 datab[12] => op_8.IN11 datab[12] => op_9.IN11 datab[12] => op_10.IN11 datab[12] => op_11.IN11 datab[12] => romout[0][12].IN1 datab[12] => romout[1][12].IN1 datab[12] => op_1.IN9 datab[12] => op_3.IN9 datab[12] => romout[0][13].IN1 datab[12] => romout[1][13].IN1 datab[12] => op_2.IN6 datab[12] => op_3.IN6 datab[12] => romout[0][14].IN1 datab[12] => romout[1][14].IN1 datab[12] => op_5.IN4 datab[12] => romout[0][15].IN1 datab[12] => romout[1][15].IN1 datab[12] => romout[2][12].IN1 datab[12] => romout[2][13].IN1 datab[12] => romout[2][14].IN1 datab[12] => romout[2][15].IN1 datab[13] => op_1.IN8 datab[13] => op_2.IN9 datab[13] => op_4.IN9 datab[13] => op_5.IN9 datab[13] => op_6.IN9 datab[13] => op_7.IN9 datab[13] => op_8.IN9 datab[13] => op_9.IN9 datab[13] => op_10.IN9 datab[13] => op_11.IN9 datab[13] => romout[0][13].IN1 datab[13] => romout[1][13].IN1 datab[13] => op_1.IN7 datab[13] => op_3.IN7 datab[13] => romout[0][14].IN1 datab[13] => romout[1][14].IN1 datab[13] => op_2.IN4 datab[13] => op_3.IN4 datab[13] => romout[0][15].IN1 datab[13] => romout[1][15].IN1 datab[13] => op_5.IN2 datab[13] => romout[0][16].IN1 datab[13] => romout[1][16].IN1 datab[13] => romout[2][13].IN1 datab[13] => romout[2][14].IN1 datab[13] => romout[2][15].IN1 datab[13] => romout[2][16].IN1 clock => ~NO_FANOUT~ aclr => ~NO_FANOUT~ clken => ~NO_FANOUT~ result[0] <= mpar_add:padder.result[0] result[1] <= mpar_add:padder.result[1] result[2] <= mpar_add:padder.result[2] result[3] <= mpar_add:padder.result[3] result[4] <= mpar_add:padder.result[4] result[5] <= mpar_add:padder.result[5] result[6] <= mpar_add:padder.result[6] result[7] <= mpar_add:padder.result[7] result[8] <= mpar_add:padder.result[8] result[9] <= mpar_add:padder.result[9] result[10] <= mpar_add:padder.result[10] result[11] <= mpar_add:padder.result[11] result[12] <= mpar_add:padder.result[12] result[13] <= mpar_add:padder.result[13] result[14] <= mpar_add:padder.result[14] result[15] <= mpar_add:padder.result[15] result[16] <= mpar_add:padder.result[16] result[17] <= mpar_add:padder.result[17] result[18] <= mpar_add:padder.result[18] result[19] <= mpar_add:padder.result[19] result[20] <= mpar_add:padder.result[20] result[21] <= mpar_add:padder.result[21] result[22] <= mpar_add:padder.result[22] result[23] <= mpar_add:padder.result[23] |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder data[0][0] => mpar_add:sub_par_add.data[0][0] data[0][1] => mpar_add:sub_par_add.data[0][1] data[0][2] => mpar_add:sub_par_add.data[0][2] data[0][3] => mpar_add:sub_par_add.data[0][3] data[0][4] => lpm_add_sub:adder[0].dataa[0] data[0][5] => lpm_add_sub:adder[0].dataa[1] data[0][6] => lpm_add_sub:adder[0].dataa[2] data[0][7] => lpm_add_sub:adder[0].dataa[3] data[0][8] => lpm_add_sub:adder[0].dataa[4] data[0][9] => lpm_add_sub:adder[0].dataa[5] data[0][10] => lpm_add_sub:adder[0].dataa[6] data[0][11] => lpm_add_sub:adder[0].dataa[7] data[0][12] => lpm_add_sub:adder[0].dataa[8] data[0][13] => lpm_add_sub:adder[0].dataa[9] data[0][14] => lpm_add_sub:adder[0].dataa[10] data[0][15] => lpm_add_sub:adder[0].dataa[11] data[0][16] => lpm_add_sub:adder[0].dataa[12] data[0][17] => lpm_add_sub:adder[0].dataa[13] data[1][0] => lpm_add_sub:adder[0].datab[0] data[1][1] => lpm_add_sub:adder[0].datab[1] data[1][2] => lpm_add_sub:adder[0].datab[2] data[1][3] => lpm_add_sub:adder[0].datab[3] data[1][4] => lpm_add_sub:adder[0].datab[4] data[1][5] => lpm_add_sub:adder[0].datab[5] data[1][6] => lpm_add_sub:adder[0].datab[6] data[1][7] => lpm_add_sub:adder[0].datab[7] data[1][8] => lpm_add_sub:adder[0].datab[8] data[1][9] => lpm_add_sub:adder[0].datab[9] data[1][10] => lpm_add_sub:adder[0].datab[10] data[1][11] => lpm_add_sub:adder[0].datab[11] data[1][12] => lpm_add_sub:adder[0].datab[12] data[1][13] => lpm_add_sub:adder[0].datab[13] data[1][14] => lpm_add_sub:adder[0].datab[14] data[1][15] => lpm_add_sub:adder[0].datab[15] data[1][16] => lpm_add_sub:adder[0].datab[16] data[1][17] => lpm_add_sub:adder[0].datab[17] data[2][0] => mpar_add:sub_par_add.data[1][0] data[2][1] => mpar_add:sub_par_add.data[1][1] data[2][2] => mpar_add:sub_par_add.data[1][2] data[2][3] => mpar_add:sub_par_add.data[1][3] data[2][4] => mpar_add:sub_par_add.data[1][4] data[2][5] => mpar_add:sub_par_add.data[1][5] data[2][6] => mpar_add:sub_par_add.data[1][6] data[2][7] => mpar_add:sub_par_add.data[1][7] data[2][8] => mpar_add:sub_par_add.data[1][8] data[2][9] => mpar_add:sub_par_add.data[1][9] data[2][10] => mpar_add:sub_par_add.data[1][10] data[2][11] => mpar_add:sub_par_add.data[1][11] data[2][12] => mpar_add:sub_par_add.data[1][12] data[2][13] => mpar_add:sub_par_add.data[1][13] data[2][14] => mpar_add:sub_par_add.data[1][14] data[2][15] => mpar_add:sub_par_add.data[1][15] data[2][16] => mpar_add:sub_par_add.data[1][16] data[2][17] => mpar_add:sub_par_add.data[1][17] cin => ~NO_FANOUT~ clk => ~NO_FANOUT~ aclr => ~NO_FANOUT~ clken => ~NO_FANOUT~ result[0] <= mpar_add:sub_par_add.result[0] result[1] <= mpar_add:sub_par_add.result[1] result[2] <= mpar_add:sub_par_add.result[2] result[3] <= mpar_add:sub_par_add.result[3] result[4] <= mpar_add:sub_par_add.result[4] result[5] <= mpar_add:sub_par_add.result[5] result[6] <= mpar_add:sub_par_add.result[6] result[7] <= mpar_add:sub_par_add.result[7] result[8] <= mpar_add:sub_par_add.result[8] result[9] <= mpar_add:sub_par_add.result[9] result[10] <= mpar_add:sub_par_add.result[10] result[11] <= mpar_add:sub_par_add.result[11] result[12] <= mpar_add:sub_par_add.result[12] result[13] <= mpar_add:sub_par_add.result[13] result[14] <= mpar_add:sub_par_add.result[14] result[15] <= mpar_add:sub_par_add.result[15] result[16] <= mpar_add:sub_par_add.result[16] result[17] <= mpar_add:sub_par_add.result[17] result[18] <= mpar_add:sub_par_add.result[18] result[19] <= mpar_add:sub_par_add.result[19] result[20] <= mpar_add:sub_par_add.result[20] result[21] <= mpar_add:sub_par_add.result[21] result[22] <= mpar_add:sub_par_add.result[22] result[23] <= mpar_add:sub_par_add.result[23] result[24] <= mpar_add:sub_par_add.result[24] result[25] <= mpar_add:sub_par_add.result[25] result[26] <= mpar_add:sub_par_add.result[26] result[27] <= mpar_add:sub_par_add.result[27] result[28] <= mpar_add:sub_par_add.result[28] result[29] <= mpar_add:sub_par_add.result[29] clk_out <= aclr_out <= clken_out <= |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] dataa[0] => add_sub_d9h:auto_generated.dataa[0] dataa[1] => add_sub_d9h:auto_generated.dataa[1] dataa[2] => add_sub_d9h:auto_generated.dataa[2] dataa[3] => add_sub_d9h:auto_generated.dataa[3] dataa[4] => add_sub_d9h:auto_generated.dataa[4] dataa[5] => add_sub_d9h:auto_generated.dataa[5] dataa[6] => add_sub_d9h:auto_generated.dataa[6] dataa[7] => add_sub_d9h:auto_generated.dataa[7] dataa[8] => add_sub_d9h:auto_generated.dataa[8] dataa[9] => add_sub_d9h:auto_generated.dataa[9] dataa[10] => add_sub_d9h:auto_generated.dataa[10] dataa[11] => add_sub_d9h:auto_generated.dataa[11] dataa[12] => add_sub_d9h:auto_generated.dataa[12] dataa[13] => add_sub_d9h:auto_generated.dataa[13] dataa[14] => add_sub_d9h:auto_generated.dataa[14] dataa[15] => add_sub_d9h:auto_generated.dataa[15] dataa[16] => add_sub_d9h:auto_generated.dataa[16] dataa[17] => add_sub_d9h:auto_generated.dataa[17] datab[0] => add_sub_d9h:auto_generated.datab[0] datab[1] => add_sub_d9h:auto_generated.datab[1] datab[2] => add_sub_d9h:auto_generated.datab[2] datab[3] => add_sub_d9h:auto_generated.datab[3] datab[4] => add_sub_d9h:auto_generated.datab[4] datab[5] => add_sub_d9h:auto_generated.datab[5] datab[6] => add_sub_d9h:auto_generated.datab[6] datab[7] => add_sub_d9h:auto_generated.datab[7] datab[8] => add_sub_d9h:auto_generated.datab[8] datab[9] => add_sub_d9h:auto_generated.datab[9] datab[10] => add_sub_d9h:auto_generated.datab[10] datab[11] => add_sub_d9h:auto_generated.datab[11] datab[12] => add_sub_d9h:auto_generated.datab[12] datab[13] => add_sub_d9h:auto_generated.datab[13] datab[14] => add_sub_d9h:auto_generated.datab[14] datab[15] => add_sub_d9h:auto_generated.datab[15] datab[16] => add_sub_d9h:auto_generated.datab[16] datab[17] => add_sub_d9h:auto_generated.datab[17] cin => ~NO_FANOUT~ add_sub => ~NO_FANOUT~ clock => ~NO_FANOUT~ aclr => ~NO_FANOUT~ clken => ~NO_FANOUT~ result[0] <= add_sub_d9h:auto_generated.result[0] result[1] <= add_sub_d9h:auto_generated.result[1] result[2] <= add_sub_d9h:auto_generated.result[2] result[3] <= add_sub_d9h:auto_generated.result[3] result[4] <= add_sub_d9h:auto_generated.result[4] result[5] <= add_sub_d9h:auto_generated.result[5] result[6] <= add_sub_d9h:auto_generated.result[6] result[7] <= add_sub_d9h:auto_generated.result[7] result[8] <= add_sub_d9h:auto_generated.result[8] result[9] <= add_sub_d9h:auto_generated.result[9] result[10] <= add_sub_d9h:auto_generated.result[10] result[11] <= add_sub_d9h:auto_generated.result[11] result[12] <= add_sub_d9h:auto_generated.result[12] result[13] <= add_sub_d9h:auto_generated.result[13] result[14] <= add_sub_d9h:auto_generated.result[14] result[15] <= add_sub_d9h:auto_generated.result[15] result[16] <= add_sub_d9h:auto_generated.result[16] result[17] <= add_sub_d9h:auto_generated.result[17] cout <= overflow <= |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_d9h:auto_generated dataa[0] => op_1.IN34 dataa[1] => op_1.IN32 dataa[2] => op_1.IN30 dataa[3] => op_1.IN28 dataa[4] => op_1.IN26 dataa[5] => op_1.IN24 dataa[6] => op_1.IN22 dataa[7] => op_1.IN20 dataa[8] => op_1.IN18 dataa[9] => op_1.IN16 dataa[10] => op_1.IN14 dataa[11] => op_1.IN12 dataa[12] => op_1.IN10 dataa[13] => op_1.IN8 dataa[14] => op_1.IN6 dataa[15] => op_1.IN4 dataa[16] => op_1.IN2 dataa[17] => op_1.IN0 datab[0] => op_1.IN35 datab[1] => op_1.IN33 datab[2] => op_1.IN31 datab[3] => op_1.IN29 datab[4] => op_1.IN27 datab[5] => op_1.IN25 datab[6] => op_1.IN23 datab[7] => op_1.IN21 datab[8] => op_1.IN19 datab[9] => op_1.IN17 datab[10] => op_1.IN15 datab[11] => op_1.IN13 datab[12] => op_1.IN11 datab[13] => op_1.IN9 datab[14] => op_1.IN7 datab[15] => op_1.IN5 datab[16] => op_1.IN3 datab[17] => op_1.IN1 result[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[9] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[10] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[11] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[12] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[13] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[14] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[15] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[16] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[17] <= op_1.DB_MAX_OUTPUT_PORT_TYPE |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add data[0][0] => result[0].DATAIN data[0][1] => result[1].DATAIN data[0][2] => result[2].DATAIN data[0][3] => result[3].DATAIN data[0][4] => result[4].DATAIN data[0][5] => result[5].DATAIN data[0][6] => result[6].DATAIN data[0][7] => result[7].DATAIN data[0][8] => lpm_add_sub:adder[0].dataa[0] data[0][9] => lpm_add_sub:adder[0].dataa[1] data[0][10] => lpm_add_sub:adder[0].dataa[2] data[0][11] => lpm_add_sub:adder[0].dataa[3] data[0][12] => lpm_add_sub:adder[0].dataa[4] data[0][13] => lpm_add_sub:adder[0].dataa[5] data[0][14] => lpm_add_sub:adder[0].dataa[6] data[0][15] => lpm_add_sub:adder[0].dataa[7] data[0][16] => lpm_add_sub:adder[0].dataa[8] data[0][17] => lpm_add_sub:adder[0].dataa[9] data[0][18] => lpm_add_sub:adder[0].dataa[10] data[0][19] => lpm_add_sub:adder[0].dataa[11] data[0][20] => lpm_add_sub:adder[0].dataa[12] data[0][21] => lpm_add_sub:adder[0].dataa[13] data[1][0] => lpm_add_sub:adder[0].datab[0] data[1][1] => lpm_add_sub:adder[0].datab[1] data[1][2] => lpm_add_sub:adder[0].datab[2] data[1][3] => lpm_add_sub:adder[0].datab[3] data[1][4] => lpm_add_sub:adder[0].datab[4] data[1][5] => lpm_add_sub:adder[0].datab[5] data[1][6] => lpm_add_sub:adder[0].datab[6] data[1][7] => lpm_add_sub:adder[0].datab[7] data[1][8] => lpm_add_sub:adder[0].datab[8] data[1][9] => lpm_add_sub:adder[0].datab[9] data[1][10] => lpm_add_sub:adder[0].datab[10] data[1][11] => lpm_add_sub:adder[0].datab[11] data[1][12] => lpm_add_sub:adder[0].datab[12] data[1][13] => lpm_add_sub:adder[0].datab[13] data[1][14] => lpm_add_sub:adder[0].datab[14] data[1][15] => lpm_add_sub:adder[0].datab[15] data[1][16] => lpm_add_sub:adder[0].datab[16] data[1][17] => lpm_add_sub:adder[0].datab[17] data[1][18] => ~NO_FANOUT~ data[1][19] => ~NO_FANOUT~ data[1][20] => ~NO_FANOUT~ data[1][21] => ~NO_FANOUT~ cin => ~NO_FANOUT~ clk => clk_out.IN0 aclr => aclr_out.IN0 clken => clken_out.IN0 result[0] <= data[0][0].DB_MAX_OUTPUT_PORT_TYPE result[1] <= data[0][1].DB_MAX_OUTPUT_PORT_TYPE result[2] <= data[0][2].DB_MAX_OUTPUT_PORT_TYPE result[3] <= data[0][3].DB_MAX_OUTPUT_PORT_TYPE result[4] <= data[0][4].DB_MAX_OUTPUT_PORT_TYPE result[5] <= data[0][5].DB_MAX_OUTPUT_PORT_TYPE result[6] <= data[0][6].DB_MAX_OUTPUT_PORT_TYPE result[7] <= data[0][7].DB_MAX_OUTPUT_PORT_TYPE result[8] <= level_result_node[0][0].DB_MAX_OUTPUT_PORT_TYPE result[9] <= level_result_node[0][1].DB_MAX_OUTPUT_PORT_TYPE result[10] <= level_result_node[0][2].DB_MAX_OUTPUT_PORT_TYPE result[11] <= level_result_node[0][3].DB_MAX_OUTPUT_PORT_TYPE result[12] <= level_result_node[0][4].DB_MAX_OUTPUT_PORT_TYPE result[13] <= level_result_node[0][5].DB_MAX_OUTPUT_PORT_TYPE result[14] <= level_result_node[0][6].DB_MAX_OUTPUT_PORT_TYPE result[15] <= level_result_node[0][7].DB_MAX_OUTPUT_PORT_TYPE result[16] <= level_result_node[0][8].DB_MAX_OUTPUT_PORT_TYPE result[17] <= level_result_node[0][9].DB_MAX_OUTPUT_PORT_TYPE result[18] <= level_result_node[0][10].DB_MAX_OUTPUT_PORT_TYPE result[19] <= level_result_node[0][11].DB_MAX_OUTPUT_PORT_TYPE result[20] <= level_result_node[0][12].DB_MAX_OUTPUT_PORT_TYPE result[21] <= level_result_node[0][13].DB_MAX_OUTPUT_PORT_TYPE result[22] <= level_result_node[0][14].DB_MAX_OUTPUT_PORT_TYPE result[23] <= level_result_node[0][15].DB_MAX_OUTPUT_PORT_TYPE result[24] <= level_result_node[0][16].DB_MAX_OUTPUT_PORT_TYPE result[25] <= level_result_node[0][17].DB_MAX_OUTPUT_PORT_TYPE result[26] <= level_result_node[0][18].DB_MAX_OUTPUT_PORT_TYPE result[27] <= level_result_node[0][19].DB_MAX_OUTPUT_PORT_TYPE result[28] <= level_result_node[0][20].DB_MAX_OUTPUT_PORT_TYPE result[29] <= level_result_node[0][21].DB_MAX_OUTPUT_PORT_TYPE clk_out <= clk_out.DB_MAX_OUTPUT_PORT_TYPE aclr_out <= aclr_out.DB_MAX_OUTPUT_PORT_TYPE clken_out <= clken_out.DB_MAX_OUTPUT_PORT_TYPE |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] dataa[0] => add_sub_89h:auto_generated.dataa[0] dataa[1] => add_sub_89h:auto_generated.dataa[1] dataa[2] => add_sub_89h:auto_generated.dataa[2] dataa[3] => add_sub_89h:auto_generated.dataa[3] dataa[4] => add_sub_89h:auto_generated.dataa[4] dataa[5] => add_sub_89h:auto_generated.dataa[5] dataa[6] => add_sub_89h:auto_generated.dataa[6] dataa[7] => add_sub_89h:auto_generated.dataa[7] dataa[8] => add_sub_89h:auto_generated.dataa[8] dataa[9] => add_sub_89h:auto_generated.dataa[9] dataa[10] => add_sub_89h:auto_generated.dataa[10] dataa[11] => add_sub_89h:auto_generated.dataa[11] dataa[12] => add_sub_89h:auto_generated.dataa[12] dataa[13] => add_sub_89h:auto_generated.dataa[13] dataa[14] => add_sub_89h:auto_generated.dataa[14] dataa[15] => add_sub_89h:auto_generated.dataa[15] dataa[16] => add_sub_89h:auto_generated.dataa[16] dataa[17] => add_sub_89h:auto_generated.dataa[17] dataa[18] => add_sub_89h:auto_generated.dataa[18] dataa[19] => add_sub_89h:auto_generated.dataa[19] dataa[20] => add_sub_89h:auto_generated.dataa[20] dataa[21] => add_sub_89h:auto_generated.dataa[21] datab[0] => add_sub_89h:auto_generated.datab[0] datab[1] => add_sub_89h:auto_generated.datab[1] datab[2] => add_sub_89h:auto_generated.datab[2] datab[3] => add_sub_89h:auto_generated.datab[3] datab[4] => add_sub_89h:auto_generated.datab[4] datab[5] => add_sub_89h:auto_generated.datab[5] datab[6] => add_sub_89h:auto_generated.datab[6] datab[7] => add_sub_89h:auto_generated.datab[7] datab[8] => add_sub_89h:auto_generated.datab[8] datab[9] => add_sub_89h:auto_generated.datab[9] datab[10] => add_sub_89h:auto_generated.datab[10] datab[11] => add_sub_89h:auto_generated.datab[11] datab[12] => add_sub_89h:auto_generated.datab[12] datab[13] => add_sub_89h:auto_generated.datab[13] datab[14] => add_sub_89h:auto_generated.datab[14] datab[15] => add_sub_89h:auto_generated.datab[15] datab[16] => add_sub_89h:auto_generated.datab[16] datab[17] => add_sub_89h:auto_generated.datab[17] datab[18] => add_sub_89h:auto_generated.datab[18] datab[19] => add_sub_89h:auto_generated.datab[19] datab[20] => add_sub_89h:auto_generated.datab[20] datab[21] => add_sub_89h:auto_generated.datab[21] cin => ~NO_FANOUT~ add_sub => ~NO_FANOUT~ clock => ~NO_FANOUT~ aclr => ~NO_FANOUT~ clken => ~NO_FANOUT~ result[0] <= add_sub_89h:auto_generated.result[0] result[1] <= add_sub_89h:auto_generated.result[1] result[2] <= add_sub_89h:auto_generated.result[2] result[3] <= add_sub_89h:auto_generated.result[3] result[4] <= add_sub_89h:auto_generated.result[4] result[5] <= add_sub_89h:auto_generated.result[5] result[6] <= add_sub_89h:auto_generated.result[6] result[7] <= add_sub_89h:auto_generated.result[7] result[8] <= add_sub_89h:auto_generated.result[8] result[9] <= add_sub_89h:auto_generated.result[9] result[10] <= add_sub_89h:auto_generated.result[10] result[11] <= add_sub_89h:auto_generated.result[11] result[12] <= add_sub_89h:auto_generated.result[12] result[13] <= add_sub_89h:auto_generated.result[13] result[14] <= add_sub_89h:auto_generated.result[14] result[15] <= add_sub_89h:auto_generated.result[15] result[16] <= add_sub_89h:auto_generated.result[16] result[17] <= add_sub_89h:auto_generated.result[17] result[18] <= add_sub_89h:auto_generated.result[18] result[19] <= add_sub_89h:auto_generated.result[19] result[20] <= add_sub_89h:auto_generated.result[20] result[21] <= add_sub_89h:auto_generated.result[21] cout <= overflow <= |ex15|const_mult:mult|lpm_mult:lpm_mult_component|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_89h:auto_generated dataa[0] => op_1.IN42 dataa[1] => op_1.IN40 dataa[2] => op_1.IN38 dataa[3] => op_1.IN36 dataa[4] => op_1.IN34 dataa[5] => op_1.IN32 dataa[6] => op_1.IN30 dataa[7] => op_1.IN28 dataa[8] => op_1.IN26 dataa[9] => op_1.IN24 dataa[10] => op_1.IN22 dataa[11] => op_1.IN20 dataa[12] => op_1.IN18 dataa[13] => op_1.IN16 dataa[14] => op_1.IN14 dataa[15] => op_1.IN12 dataa[16] => op_1.IN10 dataa[17] => op_1.IN8 dataa[18] => op_1.IN6 dataa[19] => op_1.IN4 dataa[20] => op_1.IN2 dataa[21] => op_1.IN0 datab[0] => op_1.IN43 datab[1] => op_1.IN41 datab[2] => op_1.IN39 datab[3] => op_1.IN37 datab[4] => op_1.IN35 datab[5] => op_1.IN33 datab[6] => op_1.IN31 datab[7] => op_1.IN29 datab[8] => op_1.IN27 datab[9] => op_1.IN25 datab[10] => op_1.IN23 datab[11] => op_1.IN21 datab[12] => op_1.IN19 datab[13] => op_1.IN17 datab[14] => op_1.IN15 datab[15] => op_1.IN13 datab[16] => op_1.IN11 datab[17] => op_1.IN9 datab[18] => op_1.IN7 datab[19] => op_1.IN5 datab[20] => op_1.IN3 datab[21] => op_1.IN1 result[0] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[1] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[2] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[3] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[4] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[5] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[6] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[7] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[8] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[9] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[10] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[11] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[12] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[13] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[14] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[15] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[16] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[17] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[18] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[19] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[20] <= op_1.DB_MAX_OUTPUT_PORT_TYPE result[21] <= op_1.DB_MAX_OUTPUT_PORT_TYPE |ex15|const_mult:mult|lpm_mult:lpm_mult_component|altshift:external_latency_ffs data[0] => result[0].DATAIN data[1] => result[1].DATAIN data[2] => result[2].DATAIN data[3] => result[3].DATAIN data[4] => result[4].DATAIN data[5] => result[5].DATAIN data[6] => result[6].DATAIN data[7] => result[7].DATAIN data[8] => result[8].DATAIN data[9] => result[9].DATAIN data[10] => result[10].DATAIN data[11] => result[11].DATAIN data[12] => result[12].DATAIN data[13] => result[13].DATAIN data[14] => result[14].DATAIN data[15] => result[15].DATAIN data[16] => result[16].DATAIN data[17] => result[17].DATAIN data[18] => result[18].DATAIN data[19] => result[19].DATAIN data[20] => result[20].DATAIN data[21] => result[21].DATAIN data[22] => result[22].DATAIN data[23] => result[23].DATAIN clock => ~NO_FANOUT~ aclr => ~NO_FANOUT~ clken => ~NO_FANOUT~ result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE result[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE result[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE result[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE result[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE result[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE result[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE result[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE result[8] <= data[8].DB_MAX_OUTPUT_PORT_TYPE result[9] <= data[9].DB_MAX_OUTPUT_PORT_TYPE result[10] <= data[10].DB_MAX_OUTPUT_PORT_TYPE result[11] <= data[11].DB_MAX_OUTPUT_PORT_TYPE result[12] <= data[12].DB_MAX_OUTPUT_PORT_TYPE result[13] <= data[13].DB_MAX_OUTPUT_PORT_TYPE result[14] <= data[14].DB_MAX_OUTPUT_PORT_TYPE result[15] <= data[15].DB_MAX_OUTPUT_PORT_TYPE result[16] <= data[16].DB_MAX_OUTPUT_PORT_TYPE result[17] <= data[17].DB_MAX_OUTPUT_PORT_TYPE result[18] <= data[18].DB_MAX_OUTPUT_PORT_TYPE result[19] <= data[19].DB_MAX_OUTPUT_PORT_TYPE result[20] <= data[20].DB_MAX_OUTPUT_PORT_TYPE result[21] <= data[21].DB_MAX_OUTPUT_PORT_TYPE result[22] <= data[22].DB_MAX_OUTPUT_PORT_TYPE result[23] <= data[23].DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd B[0] => BCD_0[0].DATAIN B[1] => w29[0].IN1 B[2] => w25[0].IN1 B[3] => w21[0].IN1 B[4] => w17[0].IN1 B[5] => w14[0].IN1 B[6] => w11[0].IN1 B[7] => w8[0].IN1 B[8] => w6[0].IN1 B[9] => w4[0].IN1 B[10] => w2[0].IN1 B[11] => w1[0].IN1 B[12] => w1[1].IN1 B[13] => w1[2].IN1 B[14] => w1[3].IN1 B[15] => w3[2].IN1 BCD_0[0] <= B[0].DB_MAX_OUTPUT_PORT_TYPE BCD_0[1] <= add3_ge5:A29.port1 BCD_0[2] <= add3_ge5:A29.port1 BCD_0[3] <= add3_ge5:A29.port1 BCD_1[0] <= add3_ge5:A29.port1 BCD_1[1] <= add3_ge5:A28.port1 BCD_1[2] <= add3_ge5:A28.port1 BCD_1[3] <= add3_ge5:A28.port1 BCD_2[0] <= add3_ge5:A28.port1 BCD_2[1] <= add3_ge5:A27.port1 BCD_2[2] <= add3_ge5:A27.port1 BCD_2[3] <= add3_ge5:A27.port1 BCD_3[0] <= add3_ge5:A27.port1 BCD_3[1] <= add3_ge5:A26.port1 BCD_3[2] <= add3_ge5:A26.port1 BCD_3[3] <= add3_ge5:A26.port1 BCD_4[0] <= add3_ge5:A26.port1 BCD_4[1] <= add3_ge5:A22.port1 BCD_4[2] <= add3_ge5:A18.port1 BCD_4[3] <= |ex15|bin2bcd_16:bcd|add3_ge5:A1 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A2 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A3 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A4 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A5 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A6 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A7 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A8 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A9 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A10 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A11 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A12 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A13 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A14 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A15 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A16 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A17 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A18 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A19 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A20 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A21 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A22 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A23 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A24 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A25 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A26 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A27 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A28 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|bin2bcd_16:bcd|add3_ge5:A29 w[0] => Decoder0.IN3 w[1] => Decoder0.IN2 w[2] => Decoder0.IN1 w[3] => Decoder0.IN0 a[0] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE a[1] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE a[2] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE a[3] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE |ex15|hex_to_7seg:h0 out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE in[0] => Decoder0.IN3 in[1] => Decoder0.IN2 in[2] => Decoder0.IN1 in[3] => Decoder0.IN0 |ex15|hex_to_7seg:h1 out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE in[0] => Decoder0.IN3 in[1] => Decoder0.IN2 in[2] => Decoder0.IN1 in[3] => Decoder0.IN0 |ex15|hex_to_7seg:h2 out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE in[0] => Decoder0.IN3 in[1] => Decoder0.IN2 in[2] => Decoder0.IN1 in[3] => Decoder0.IN0 |ex15|hex_to_7seg:h3 out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE in[0] => Decoder0.IN3 in[1] => Decoder0.IN2 in[2] => Decoder0.IN1 in[3] => Decoder0.IN0 |ex15|hex_to_7seg:h4 out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE in[0] => Decoder0.IN3 in[1] => Decoder0.IN2 in[2] => Decoder0.IN1 in[3] => Decoder0.IN0