MipsCPU - Cycle accurate MIPS CPU simulation.

	Commit message (Collapse)	Author	Age	Files	Lines
*	adding more instructions to the test cases and the cpu	zedarider	2016-10-25	8	-75/+520
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*	cleaned up	zedarider	2016-10-17	3	-5/+5
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*	added bitwise operators	zedarider	2016-10-17	7	-13/+90
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*	fully working add and sub	zedarider	2016-10-17	7	-80/+108
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*	adding all initial files	zedarider	2016-10-14	9	-0/+314
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*	Updated for 2016.	David Thomas	2016-10-10	3	-267/+11
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*	Modified description of LH and LHU. Thanks to @roastedpork. Closes #8.	m8pple	2015-10-22	1	-2/+2
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*	Added JALR to sg_instructionsArray. Closes #7.	m8pple	2015-10-20	1	-0/+1
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*	Converted %lf to %f in relation to issue #5.	m8pple	2015-10-19	1	-4/+4
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*	Adding example eie2ugs code from live tutorial + recorded tutorial:	m8pple	2015-10-19	2	-0/+259
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*	Update for 2015.	m8pple	2015-10-12	3	-132/+5
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*	Fix for issue #15	OJFord	2014-10-23	1	-1/+1
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*	Very basic skeleton from the classes.	m8pple	2014-10-20	2	-0/+132
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*	Initial push.	m8pple	2014-10-16	2	-0/+346