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| author | Yann Herklotz <git@yannherklotz.com> | 2022-11-24 22:19:33 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2022-11-24 22:19:33 +0000 |
| commit | c0056cea555efe0d6775e3b28ffa5a4a91293097 (patch) | |
| tree | 9c7c419249ebfefffac32f2acdf61eacb790f99c | |
| parent | 0abf2303ac89dd0d0ad88bd7f0bc0a45ffc04ff1 (diff) | |
| download | butterstick-c0056cea555efe0d6775e3b28ffa5a4a91293097.tar.gz butterstick-c0056cea555efe0d6775e3b28ffa5a4a91293097.zip | |
Fix simulation
| -rw-r--r-- | Makefile | 8 | ||||
| -rw-r--r-- | example_tb.v | 7 |
2 files changed, 7 insertions, 8 deletions
@@ -1,6 +1,6 @@ TOOLCHAIN_PREFIX = /opt/riscv32i/bin/riscv32-unknown-elf- -ICE40_SIM_CELLS=$(shell yosys-config --datdir/ecp5/cells_sim.v) +ECP5_SIM_CELLS=$(shell yosys-config --datdir/ecp5/cells_sim.v) COPY=cp # set to 4 for simulation @@ -48,7 +48,7 @@ example.bit: example_out.config ## ----------------- ## icarus simulation -example_tb.vvp: example.v example_tb.v ../../picorv32.v firmware.hex +example_tb.vvp: example.v example_tb.v picorv32/picorv32.v firmware.hex iverilog -o $@ -s testbench $(filter %.v, $^) chmod -x $@ @@ -62,7 +62,7 @@ example_sim_vcd: example_tb.vvp ## post-synth simulation synth_tb.vvp: example_tb.v synth.json - iverilog -o $@ -s testbench synth.v example_tb.v $(ICE40_SIM_CELLS) + iverilog -o $@ -s testbench synth.v example_tb.v $(ECP5_SIM_CELLS) chmod -x $@ synth_sim: synth_tb.vvp @@ -78,7 +78,7 @@ route.v: example.asc example.pcf icebox_vlog -L -n top -sp example.pcf $< > $@ route_tb.vvp: route.v example_tb.v - iverilog -o $@ -s testbench $^ $(ICE40_SIM_CELLS) + iverilog -o $@ -s testbench $^ $(ECP5_SIM_CELLS) chmod -x $@ route_sim: route_tb.vvp diff --git a/example_tb.v b/example_tb.v index f04f8f8..e4b55a1 100644 --- a/example_tb.v +++ b/example_tb.v @@ -3,7 +3,7 @@ module testbench; reg clk = 1; always #5 clk = ~clk; - wire LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7; + wire LED0, LED1, LED2, LED3, LED4, LED5, LED6; top uut ( .clk(clk), @@ -13,8 +13,7 @@ module testbench; .LED3(LED3), .LED4(LED4), .LED5(LED5), - .LED6(LED6), - .LED7(LED7) + .LED6(LED6) ); initial begin @@ -23,7 +22,7 @@ module testbench; $dumpvars(0, testbench); end - $monitor(LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0); + $monitor(LED6, LED5, LED4, LED3, LED2, LED1, LED0); repeat (10000) @(posedge clk); $finish; end |