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| author | Yann Herklotz <git@yannherklotz.com> | 2022-11-24 18:49:44 +0000 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2022-11-24 18:49:44 +0000 |
| commit | 46c49262fc9910ba5ff92e76d567ed2e4446fb41 (patch) | |
| tree | 5bc1955e8fbf29ea454a0db3db1eaf4955e2ca28 /picorv32/tests/bne.S | |
| parent | 08cf3d9a31b8acbf679b3c761edc95f3d27f7e2a (diff) | |
| parent | 3291d86ec38031e191ec1e7e5e8ddfa74b77cb7c (diff) | |
| download | butterstick-46c49262fc9910ba5ff92e76d567ed2e4446fb41.tar.gz butterstick-46c49262fc9910ba5ff92e76d567ed2e4446fb41.zip | |
Merge commit '3291d86ec38031e191ec1e7e5e8ddfa74b77cb7c' as 'picorv32'
Diffstat (limited to 'picorv32/tests/bne.S')
| -rw-r--r-- | picorv32/tests/bne.S | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/picorv32/tests/bne.S b/picorv32/tests/bne.S new file mode 100644 index 0000000..0b33753 --- /dev/null +++ b/picorv32/tests/bne.S @@ -0,0 +1,73 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bne.S +#----------------------------------------------------------------------------- +# +# Test bne instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, bne, 0, 1 ); + TEST_BR2_OP_TAKEN( 3, bne, 1, 0 ); + TEST_BR2_OP_TAKEN( 4, bne, -1, 1 ); + TEST_BR2_OP_TAKEN( 5, bne, 1, -1 ); + + TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 ); + TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 ); + TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 9, 0, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 ); + + TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 21, x1, 3, \ + li x1, 1; \ + bne x1, x0, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END |