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author | Yann Herklotz <git@yannherklotz.com> | 2022-11-24 18:49:44 +0000 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2022-11-24 18:49:44 +0000 |
commit | 3291d86ec38031e191ec1e7e5e8ddfa74b77cb7c (patch) | |
tree | 7d604206a2deb29c9f097ff1f3b7de78f44b34a3 /scripts/yosys/synth_sim.ys | |
download | butterstick-3291d86ec38031e191ec1e7e5e8ddfa74b77cb7c.tar.gz butterstick-3291d86ec38031e191ec1e7e5e8ddfa74b77cb7c.zip |
Squashed 'picorv32/' content from commit f00a88c
git-subtree-dir: picorv32
git-subtree-split: f00a88c36eaab478b64ee27d8162e421049bcc66
Diffstat (limited to 'scripts/yosys/synth_sim.ys')
-rw-r--r-- | scripts/yosys/synth_sim.ys | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/scripts/yosys/synth_sim.ys b/scripts/yosys/synth_sim.ys new file mode 100644 index 0000000..ded89d9 --- /dev/null +++ b/scripts/yosys/synth_sim.ys @@ -0,0 +1,8 @@ +# yosys synthesis script for post-synthesis simulation (make test_synth) + +read_verilog picorv32.v +chparam -set COMPRESSED_ISA 1 -set ENABLE_MUL 1 -set ENABLE_DIV 1 \ + -set ENABLE_IRQ 1 -set ENABLE_TRACE 1 picorv32_axi +hierarchy -top picorv32_axi +synth +write_verilog synth.v |