Squashed 'picorv32/' content from commit f00a88c

git-subtree-dir: picorv32
git-subtree-split: f00a88c36eaab478b64ee27d8162e421049bcc66

6 files changed, 99 insertions, 0 deletions

diff --git a/scripts/yosys/.gitignore b/scripts/yosys/.gitignore
new file mode 100644
index 0000000..d6fc3e3
--- /dev/null
+++ b/scripts/yosys/.gitignore
@@ -0,0 +1 @@
+osu018_stdcells.lib
diff --git a/scripts/yosys/synth_gates.lib b/scripts/yosys/synth_gates.lib
new file mode 100644
index 0000000..be706dd
--- /dev/null
+++ b/scripts/yosys/synth_gates.lib
@@ -0,0 +1,38 @@
+library(gates) {
+  cell(NOT) {
+    area: 2; // 7404 hex inverter
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A'"; }
+  }
+  cell(BUF) {
+    area: 4; // 2x 7404 hex inverter
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A"; }
+  }
+  cell(NAND) {
+    area: 3; // 7400 quad 2-input NAND gate
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A*B)'"; }
+  }
+  cell(NOR) {
+    area: 3; // 7402 quad 2-input NOR gate
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A+B)'"; }
+  }
+  cell(DFF) {
+    area: 6; // 7474 dual D positive edge triggered flip-flop
+    ff(IQ, IQN) { clocked_on: C;
+                  next_state: D; }
+    pin(C) { direction: input;
+                 clock: true; }
+    pin(D) { direction: input; }
+    pin(Q) { direction: output;
+              function: "IQ"; }
+  }
+}
diff --git a/scripts/yosys/synth_gates.v b/scripts/yosys/synth_gates.v
new file mode 100644
index 0000000..8e2504e
--- /dev/null
+++ b/scripts/yosys/synth_gates.v
@@ -0,0 +1,30 @@
+module top (
+	input clk, resetn,
+
+	output        mem_valid,
+	output        mem_instr,
+	input         mem_ready,
+
+	output [31:0] mem_addr,
+	output [31:0] mem_wdata,
+	output [ 3:0] mem_wstrb,
+	input  [31:0] mem_rdata
+);
+	picorv32 #(
+		.ENABLE_COUNTERS(0),
+		.LATCHED_MEM_RDATA(1),
+		.TWO_STAGE_SHIFT(0),
+		.CATCH_MISALIGN(0),
+		.CATCH_ILLINSN(0)
+	) picorv32 (
+		.clk      (clk      ),
+		.resetn   (resetn   ),
+		.mem_valid(mem_valid),
+		.mem_instr(mem_instr),
+		.mem_ready(mem_ready),
+		.mem_addr (mem_addr ),
+		.mem_wdata(mem_wdata),
+		.mem_wstrb(mem_wstrb),
+		.mem_rdata(mem_rdata)
+	);
+endmodule
diff --git a/scripts/yosys/synth_gates.ys b/scripts/yosys/synth_gates.ys
new file mode 100644
index 0000000..311d767
--- /dev/null
+++ b/scripts/yosys/synth_gates.ys
@@ -0,0 +1,14 @@
+read_verilog synth_gates.v
+read_verilog ../../picorv32.v
+
+hierarchy -top top
+proc; flatten
+
+synth
+
+dfflibmap -prepare -liberty synth_gates.lib
+abc -dff -liberty synth_gates.lib
+dfflibmap -liberty synth_gates.lib
+
+stat
+write_blif synth_gates.blif
diff --git a/scripts/yosys/synth_osu018.sh b/scripts/yosys/synth_osu018.sh
new file mode 100644
index 0000000..7a8693d
--- /dev/null
+++ b/scripts/yosys/synth_osu018.sh
@@ -0,0 +1,8 @@
+#!/bin/bash
+set -ex
+if test ! -s osu018_stdcells.lib; then
+	wget --continue -O osu018_stdcells.lib.part http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/`
+			`latest/cadence/lib/tsmc018/signalstorm/osu018_stdcells.lib
+	mv osu018_stdcells.lib.part osu018_stdcells.lib
+fi
+yosys -p 'synth -top picorv32; dfflibmap -liberty osu018_stdcells.lib; abc -liberty osu018_stdcells.lib; stat' ../../picorv32.v
diff --git a/scripts/yosys/synth_sim.ys b/scripts/yosys/synth_sim.ys
new file mode 100644
index 0000000..ded89d9
--- /dev/null
+++ b/scripts/yosys/synth_sim.ys
@@ -0,0 +1,8 @@
+# yosys synthesis script for post-synthesis simulation (make test_synth)
+
+read_verilog picorv32.v
+chparam -set COMPRESSED_ISA 1 -set ENABLE_MUL 1 -set ENABLE_DIV 1 \
+        -set ENABLE_IRQ 1 -set ENABLE_TRACE 1 picorv32_axi
+hierarchy -top picorv32_axi
+synth
+write_verilog synth.v