254 files changed, 371 insertions, 0 deletions

diff --git a/riscv/Makefile b/riscv/Makefile
new file mode 100644
index 0000000..404edf5
--- /dev/null
+++ b/riscv/Makefile
@@ -0,0 +1,112 @@
+TOOLCHAIN_PREFIX = /opt/riscv32i/bin/riscv32-unknown-elf-
+
+ECP5_SIM_CELLS=$(shell yosys-config --datdir/ecp5/cells_sim.v)
+COPY=cp
+
+# set to 4 for simulation
+FIRMWARE_COUNTER_BITS=18
+
+all: example.dfu
+
+dfu: example.dfu
+	dfu-util --alt 0 --download $< --reset
+
+## -------------------
+## firmware generation
+
+firmware.elf: firmware.S firmware.c firmware.lds
+	$(TOOLCHAIN_PREFIX)gcc \
+		-DSHIFT_COUNTER_BITS=$(FIRMWARE_COUNTER_BITS) \
+		-march=rv32i -Os -ffreestanding -nostdlib \
+		-o $@ firmware.S firmware.c \
+		--std=gnu99 -Wl,-Bstatic,-T,firmware.lds,-Map,firmware.map,--strip-debug
+	chmod -x $@
+
+firmware.bin: firmware.elf
+	$(TOOLCHAIN_PREFIX)objcopy -O binary $< $@
+	chmod -x $@
+
+firmware.hex: firmware.bin
+	python3 picorv32/firmware/makehex.py $< 128 > $@
+
+## ------------------------------
+## main flow: synth/p&r/bitstream
+
+synth.json: example.v picorv32/picorv32.v firmware.hex
+	yosys -v3 -l synth.log -p 'synth_ecp5 -top top -json $@; write_verilog -attr2comment synth.v' $(filter %.v, $^)
+
+example_out.config: synth.json example.pcf
+	nextpnr-ecp5 --json $< --textcfg $@ --um5g-85k --speed 8 --package CABGA381 --lpf example.pcf
+
+example.bit: example_out.config
+	ecppack --compress --freq 38.8 --input $< --bit $@
+
+%.dfu : %.bit
+	$(COPY) $< $@
+	dfu-suffix -v 1209 -p 5af1 -a $@
+
+## -----------------
+## icarus simulation
+
+example_tb.vvp: example.v example_tb.v picorv32/picorv32.v firmware.hex
+	iverilog -o $@ -s testbench $(filter %.v, $^)
+	chmod -x $@
+
+example_sim: example_tb.vvp
+	vvp -N $<
+
+example_sim_vcd: example_tb.vvp
+	vvp -N $< +vcd
+
+## ---------------------
+## post-synth simulation
+
+synth_tb.vvp: example_tb.v synth.json
+	iverilog -o $@ -s testbench synth.v example_tb.v $(ECP5_SIM_CELLS)
+	chmod -x $@
+
+synth_sim: synth_tb.vvp
+	vvp -N $<
+
+synth_sim_vcd: synth_tb.vvp
+	vvp -N $< +vcd
+
+## ---------------------
+## post-route simulation
+
+route.v: example.asc example.pcf
+	icebox_vlog -L -n top -sp example.pcf $< > $@
+
+route_tb.vvp: route.v example_tb.v
+	iverilog -o $@ -s testbench $^ $(ECP5_SIM_CELLS)
+	chmod -x $@
+
+route_sim: route_tb.vvp
+	vvp -N $<
+
+route_sim_vcd: route_tb.vvp
+	vvp -N $< +vcd
+
+## ---------------------
+## miscellaneous targets
+
+prog_sram: example.bin
+	iceprog -S $<
+
+timing: example.asc example.pcf
+	icetime -c 62 -tmd hx8k -P ct256 -p example.pcf -t $<
+
+view: example.vcd
+	gtkwave $< example.gtkw
+
+## ------
+## el fin
+
+clean:
+	rm -f firmware.elf firmware.map firmware.bin firmware.hex
+	rm -f synth.log synth.v synth.json route.v example.asc example.bin
+	rm -f example_tb.vvp synth_tb.vvp route_tb.vvp example.vcd
+
+.PHONY: all prog_sram view clean
+.PHONY: example_sim synth_sim route_sim timing
+.PHONY: example_sim_vcd synth_sim_vcd route_sim_vcd
diff --git a/riscv/README.org b/riscv/README.org
new file mode 100644
index 0000000..9c549b7
--- /dev/null
+++ b/riscv/README.org
@@ -0,0 +1,19 @@
+#+title: ButterStick CPU
+#+author: Yann Herklotz
+
+To build the example LED-blinking firmware for an HX8K Breakout Board and get
+a timing report (checked against the default 12MHz oscillator):
+
+#+begin_src shell
+$ make clean example.bin timing
+#+end_src
+
+To run all the simulation tests:
+
+#+begin_src shell
+$ make clean example_sim synth_sim route_sim FIRMWARE_COUNTER_BITS=4
+#+end_src
+
+(You must run the `clean` target to rebuild the firmware with the updated
+`FIRMWARE_COUNTER_BITS` parameter; the firmware source must be recompiled for
+simulation vs hardware, but this is not tracked as a Makefile dependency.)
diff --git a/riscv/example.pcf b/riscv/example.pcf
new file mode 100644
index 0000000..6d6ff81
--- /dev/null
+++ b/riscv/example.pcf
@@ -0,0 +1,38 @@
+# This is a partial constraints file for ButterStick r1.0,
+# produced based on
+# https://github.com/butterstick-fpga/butterstick-bootloader/blob/main/gateware/rtl/platform/butterstick_r1d0.py
+# All mistakes mine, Tommy Thorn, 2021
+
+LOCATE COMP "clk" SITE "B12";
+IOBUF PORT "clk" IO_TYPE=LVCMOS18;
+FREQUENCY PORT "clk" 30.0 MHz;
+
+LOCATE COMP "rst_n" SITE "R3";
+IOBUF PORT "rst_n" IO_TYPE=LVCMOS33 OPENDRAIN=ON;
+
+LOCATE COMP "user_btn[0]" SITE "U16";
+IOBUF PORT "user_btn[0]" IO_TYPE=SSTL135_I;
+
+LOCATE COMP "user_btn[1]" SITE "T17";
+IOBUF PORT "user_btn[1]" IO_TYPE=SSTL135_I;
+
+LOCATE COMP "LED0" SITE "C13";
+IOBUF PORT "LED0" IO_TYPE=LVCMOS33;
+LOCATE COMP "LED1" SITE "D12";
+IOBUF PORT "LED1" IO_TYPE=LVCMOS33;
+LOCATE COMP "LED2" SITE "U2";
+IOBUF PORT "LED2" IO_TYPE=LVCMOS33;
+LOCATE COMP "LED3" SITE "T3";
+IOBUF PORT "LED3" IO_TYPE=LVCMOS33;
+LOCATE COMP "LED4" SITE "D13";
+IOBUF PORT "LED4" IO_TYPE=LVCMOS33;
+LOCATE COMP "LED5" SITE "E13";
+IOBUF PORT "LED5" IO_TYPE=LVCMOS33;
+LOCATE COMP "LED6" SITE "C16";
+IOBUF PORT "LED6" IO_TYPE=LVCMOS33;
+LOCATE COMP "colour[0]" SITE "T1";
+IOBUF PORT "colour[0]" IO_TYPE=LVCMOS33;
+LOCATE COMP "colour[1]" SITE "R1";
+IOBUF PORT "colour[1]" IO_TYPE=LVCMOS33;
+LOCATE COMP "colour[2]" SITE "U1";
+IOBUF PORT "colour[2]" IO_TYPE=LVCMOS33;
\ No newline at end of file
diff --git a/riscv/example.v b/riscv/example.v
new file mode 100644
index 0000000..391115b
--- /dev/null
+++ b/riscv/example.v
@@ -0,0 +1,95 @@
+`timescale 1 ns / 1 ps
+
+module top (
+	input            clk,
+	output reg       LED0, LED1, LED2, LED3, LED4, LED5, LED6,
+    output reg [2:0] colour
+);
+	// -------------------------------
+	// Reset Generator
+
+	reg [7:0] resetn_counter = 0;
+	wire resetn = &resetn_counter;
+
+	always @(posedge clk) begin
+		if (!resetn)
+			resetn_counter <= resetn_counter + 1;
+	end
+
+
+	// -------------------------------
+	// PicoRV32 Core
+
+	wire mem_valid;
+	wire [31:0] mem_addr;
+	wire [31:0] mem_wdata;
+	wire [3:0] mem_wstrb;
+
+	reg mem_ready;
+	reg [31:0] mem_rdata;
+
+	picorv32 #(
+		.ENABLE_COUNTERS(0),
+		.LATCHED_MEM_RDATA(1),
+		.TWO_STAGE_SHIFT(0),
+		.TWO_CYCLE_ALU(1),
+		.CATCH_MISALIGN(0),
+		.CATCH_ILLINSN(0)
+	) cpu (
+		.clk      (clk      ),
+		.resetn   (resetn   ),
+		.mem_valid(mem_valid),
+		.mem_ready(mem_ready),
+		.mem_addr (mem_addr ),
+		.mem_wdata(mem_wdata),
+		.mem_wstrb(mem_wstrb),
+		.mem_rdata(mem_rdata)
+	);
+
+
+	// -------------------------------
+	// Memory/IO Interface
+
+	// 128 32bit words = 512 bytes memory
+	localparam MEM_SIZE = 128;
+	reg [31:0] memory [0:MEM_SIZE-1];
+	initial $readmemh("firmware.hex", memory);
+
+	always @(posedge clk) begin
+		mem_ready <= 0;
+		if (resetn && mem_valid && !mem_ready) begin
+			(* parallel_case *)
+			case (1)
+				!mem_wstrb && (mem_addr >> 2) < MEM_SIZE: begin
+					mem_rdata <= memory[mem_addr >> 2];
+					mem_ready <= 1;
+				end
+				|mem_wstrb && (mem_addr >> 2) < MEM_SIZE: begin
+					if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
+					if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
+					if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
+					if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
+					mem_ready <= 1;
+				end
+				|mem_wstrb && mem_addr == 32'h1000_0000: begin
+					{LED6, LED5, LED4, LED3, LED2, LED1, LED0} <= mem_wdata;
+					mem_ready <= 1;
+				end
+			endcase
+		end
+	end
+
+   //always @(posedge clk) begin
+   //   LED0 <= 0;
+   //   LED1 <= 1;
+   //   LED2 <= 0;
+   //   LED3 <= 1;
+   //   LED4 <= 0;
+   //   LED5 <= 1;
+   //   LED6 <= 0;
+   //
+   //   colour[0] <= 1;
+   //   colour[2] <= 1;
+   //end
+   
+endmodule
diff --git a/riscv/example_tb.v b/riscv/example_tb.v
new file mode 100644
index 0000000..e4b55a1
--- /dev/null
+++ b/riscv/example_tb.v
@@ -0,0 +1,29 @@
+`timescale 1 ns / 1 ps
+
+module testbench;
+	reg clk = 1;
+	always #5 clk = ~clk;
+	wire LED0, LED1, LED2, LED3, LED4, LED5, LED6;
+
+	top uut (
+		.clk(clk),
+		.LED0(LED0),
+		.LED1(LED1),
+		.LED2(LED2),
+		.LED3(LED3),
+		.LED4(LED4),
+		.LED5(LED5),
+		.LED6(LED6)
+	);
+
+	initial begin
+		if ($test$plusargs("vcd")) begin
+			$dumpfile("example.vcd");
+			$dumpvars(0, testbench);
+		end
+
+		$monitor(LED6, LED5, LED4, LED3, LED2, LED1, LED0);
+		repeat (10000) @(posedge clk);
+		$finish;
+	end
+endmodule
diff --git a/scripts/icestorm/firmware.S b/riscv/firmware.S
index d19783d..d19783d 100644
--- a/scripts/icestorm/firmware.S
+++ b/riscv/firmware.S
diff --git a/riscv/firmware.c b/riscv/firmware.c
new file mode 100644
index 0000000..c39ebbd
--- /dev/null
+++ b/riscv/firmware.c
@@ -0,0 +1,55 @@
+#include <stdint.h>
+
+#ifndef SHIFT_COUNTER_BITS
+#error SHIFT_COUNTER_BITS must be defined as 4 (for simulation) or 18 (for hardware bitstreams)!
+#endif
+
+void output(uint8_t c)
+{
+	*(volatile char*)0x10000000 = c;
+}
+
+uint8_t gray_encode_simple(uint8_t c)
+{
+	return c ^ (c >> 1);
+}
+
+uint8_t gray_encode_bitwise(uint8_t c)
+{
+	unsigned int in_buf = c, out_buf = 0, bit = 1;
+	for (int i = 0; i < 8; i++) {
+		if ((in_buf & 1) ^ ((in_buf >> 1) & 1))
+			out_buf |= bit;
+		in_buf = in_buf >> 1;
+		bit = bit << 1;
+	}
+	return out_buf;
+}
+
+uint8_t gray_decode(uint8_t c)
+{
+	uint8_t t = c >> 1;
+	while (t) {
+		c = c ^ t;
+		t = t >> 1;
+	}
+	return c;
+}
+
+void gray(uint8_t c)
+{
+	uint8_t gray_simple = gray_encode_simple(c);
+	uint8_t gray_bitwise = gray_encode_bitwise(c);
+	uint8_t gray_decoded = gray_decode(gray_simple);
+
+	if (gray_simple != gray_bitwise || gray_decoded != c)
+		while (1) asm volatile ("ebreak");
+
+	output(101);
+}
+
+void main()
+{
+	while (1)
+      output(0xAA);
+}
diff --git a/scripts/icestorm/firmware.lds b/riscv/firmware.lds
index 970000a..970000a 100644
--- a/scripts/icestorm/firmware.lds
+++ b/riscv/firmware.lds
diff --git a/.gitignore b/riscv/picorv32/.gitignore
index 487adcc..487adcc 100644
--- a/.gitignore
+++ b/riscv/picorv32/.gitignore
diff --git a/COPYING b/riscv/picorv32/COPYING
index 3027e19..3027e19 100644
--- a/COPYING
+++ b/riscv/picorv32/COPYING
diff --git a/Makefile b/riscv/picorv32/Makefile
index d7027e3..d7027e3 100644
--- a/Makefile
+++ b/riscv/picorv32/Makefile
diff --git a/README.md b/riscv/picorv32/README.md
index bcd8fa1..bcd8fa1 100644
--- a/README.md
+++ b/riscv/picorv32/README.md
diff --git a/dhrystone/Makefile b/riscv/picorv32/dhrystone/Makefile
index 89cb110..89cb110 100644
--- a/dhrystone/Makefile
+++ b/riscv/picorv32/dhrystone/Makefile
diff --git a/dhrystone/README b/riscv/picorv32/dhrystone/README
index e08b25b..e08b25b 100644
--- a/dhrystone/README
+++ b/riscv/picorv32/dhrystone/README
diff --git a/dhrystone/dhry.h b/riscv/picorv32/dhrystone/dhry.h
index 41f1495..41f1495 100644
--- a/dhrystone/dhry.h
+++ b/riscv/picorv32/dhrystone/dhry.h
diff --git a/dhrystone/dhry_1.c b/riscv/picorv32/dhrystone/dhry_1.c
index fa0d4d9..fa0d4d9 100644
--- a/dhrystone/dhry_1.c
+++ b/riscv/picorv32/dhrystone/dhry_1.c
diff --git a/dhrystone/dhry_1_orig.c b/riscv/picorv32/dhrystone/dhry_1_orig.c
index 848fc5b..848fc5b 100644
--- a/dhrystone/dhry_1_orig.c
+++ b/riscv/picorv32/dhrystone/dhry_1_orig.c
diff --git a/dhrystone/dhry_2.c b/riscv/picorv32/dhrystone/dhry_2.c
index ac5be3b..ac5be3b 100644
--- a/dhrystone/dhry_2.c
+++ b/riscv/picorv32/dhrystone/dhry_2.c
diff --git a/dhrystone/sections.lds b/riscv/picorv32/dhrystone/sections.lds
index 3efb873..3efb873 100644
--- a/dhrystone/sections.lds
+++ b/riscv/picorv32/dhrystone/sections.lds
diff --git a/dhrystone/start.S b/riscv/picorv32/dhrystone/start.S
index 9fb2359..9fb2359 100644
--- a/dhrystone/start.S
+++ b/riscv/picorv32/dhrystone/start.S
diff --git a/dhrystone/stdlib.c b/riscv/picorv32/dhrystone/stdlib.c
index f88023b..f88023b 100644
--- a/dhrystone/stdlib.c
+++ b/riscv/picorv32/dhrystone/stdlib.c
diff --git a/dhrystone/syscalls.c b/riscv/picorv32/dhrystone/syscalls.c
index 8ea84ca..8ea84ca 100644
--- a/dhrystone/syscalls.c
+++ b/riscv/picorv32/dhrystone/syscalls.c
diff --git a/dhrystone/testbench.v b/riscv/picorv32/dhrystone/testbench.v
index 9c365a6..9c365a6 100644
--- a/dhrystone/testbench.v
+++ b/riscv/picorv32/dhrystone/testbench.v
diff --git a/dhrystone/testbench_nola.v b/riscv/picorv32/dhrystone/testbench_nola.v
index b1a154c..b1a154c 100644
--- a/dhrystone/testbench_nola.v
+++ b/riscv/picorv32/dhrystone/testbench_nola.v
diff --git a/firmware/README b/riscv/picorv32/firmware/README
index 2ade487..2ade487 100644
--- a/firmware/README
+++ b/riscv/picorv32/firmware/README
diff --git a/firmware/custom_ops.S b/riscv/picorv32/firmware/custom_ops.S
index 71889b9..71889b9 100644
--- a/firmware/custom_ops.S
+++ b/riscv/picorv32/firmware/custom_ops.S
diff --git a/firmware/firmware.h b/riscv/picorv32/firmware/firmware.h
index 59d3f11..59d3f11 100644
--- a/firmware/firmware.h
+++ b/riscv/picorv32/firmware/firmware.h
diff --git a/firmware/hello.c b/riscv/picorv32/firmware/hello.c
index b7e0b96..b7e0b96 100644
--- a/firmware/hello.c
+++ b/riscv/picorv32/firmware/hello.c
diff --git a/firmware/irq.c b/riscv/picorv32/firmware/irq.c
index 9fc1735..9fc1735 100644
--- a/firmware/irq.c
+++ b/riscv/picorv32/firmware/irq.c
diff --git a/firmware/makehex.py b/riscv/picorv32/firmware/makehex.py
index 419b378..419b378 100644
--- a/firmware/makehex.py
+++ b/riscv/picorv32/firmware/makehex.py
diff --git a/firmware/multest.c b/riscv/picorv32/firmware/multest.c
index 1706400..1706400 100644
--- a/firmware/multest.c
+++ b/riscv/picorv32/firmware/multest.c
diff --git a/firmware/print.c b/riscv/picorv32/firmware/print.c
index accce26..accce26 100644
--- a/firmware/print.c
+++ b/riscv/picorv32/firmware/print.c
diff --git a/firmware/riscv.ld b/riscv/picorv32/firmware/riscv.ld
index 16fde8d..16fde8d 100644
--- a/firmware/riscv.ld
+++ b/riscv/picorv32/firmware/riscv.ld
diff --git a/firmware/riscv.ld.orig b/riscv/picorv32/firmware/riscv.ld.orig
index 6d40e3d..6d40e3d 100644
--- a/firmware/riscv.ld.orig
+++ b/riscv/picorv32/firmware/riscv.ld.orig
diff --git a/firmware/sections.lds b/riscv/picorv32/firmware/sections.lds
index f914b46..f914b46 100644
--- a/firmware/sections.lds
+++ b/riscv/picorv32/firmware/sections.lds
diff --git a/firmware/sieve.c b/riscv/picorv32/firmware/sieve.c
index ff945eb..ff945eb 100644
--- a/firmware/sieve.c
+++ b/riscv/picorv32/firmware/sieve.c
diff --git a/firmware/start.S b/riscv/picorv32/firmware/start.S
index d95f04c..d95f04c 100644
--- a/firmware/start.S
+++ b/riscv/picorv32/firmware/start.S
diff --git a/firmware/stats.c b/riscv/picorv32/firmware/stats.c
index 80e22dd..80e22dd 100644
--- a/firmware/stats.c
+++ b/riscv/picorv32/firmware/stats.c
diff --git a/picorv32.core b/riscv/picorv32/picorv32.core
index 08ee704..08ee704 100644
--- a/picorv32.core
+++ b/riscv/picorv32/picorv32.core
diff --git a/picorv32.v b/riscv/picorv32/picorv32.v
index cfc7ce0..cfc7ce0 100644
--- a/picorv32.v
+++ b/riscv/picorv32/picorv32.v
diff --git a/picosoc/.gitignore b/riscv/picorv32/picosoc/.gitignore
index 4ac8239..4ac8239 100644
--- a/picosoc/.gitignore
+++ b/riscv/picorv32/picosoc/.gitignore
diff --git a/picosoc/Makefile b/riscv/picorv32/picosoc/Makefile
index 291a12d..291a12d 100644
--- a/picosoc/Makefile
+++ b/riscv/picorv32/picosoc/Makefile
diff --git a/picosoc/README.md b/riscv/picorv32/picosoc/README.md
index 1708709..1708709 100644
--- a/picosoc/README.md
+++ b/riscv/picorv32/picosoc/README.md
diff --git a/picosoc/firmware.c b/riscv/picorv32/picosoc/firmware.c
index aadf31b..aadf31b 100644
--- a/picosoc/firmware.c
+++ b/riscv/picorv32/picosoc/firmware.c
diff --git a/picosoc/hx8kdemo.core b/riscv/picorv32/picosoc/hx8kdemo.core
index 97a1989..97a1989 100644
--- a/picosoc/hx8kdemo.core
+++ b/riscv/picorv32/picosoc/hx8kdemo.core
diff --git a/picosoc/hx8kdemo.pcf b/riscv/picorv32/picosoc/hx8kdemo.pcf
index 418bae8..418bae8 100644
--- a/picosoc/hx8kdemo.pcf
+++ b/riscv/picorv32/picosoc/hx8kdemo.pcf
diff --git a/picosoc/hx8kdemo.v b/riscv/picorv32/picosoc/hx8kdemo.v
index f9a82f1..f9a82f1 100644
--- a/picosoc/hx8kdemo.v
+++ b/riscv/picorv32/picosoc/hx8kdemo.v
diff --git a/picosoc/hx8kdemo_tb.v b/riscv/picorv32/picosoc/hx8kdemo_tb.v
index 3fe9c1d..3fe9c1d 100644
--- a/picosoc/hx8kdemo_tb.v
+++ b/riscv/picorv32/picosoc/hx8kdemo_tb.v
diff --git a/picosoc/ice40up5k_spram.v b/riscv/picorv32/picosoc/ice40up5k_spram.v
index 6d010f2..6d010f2 100644
--- a/picosoc/ice40up5k_spram.v
+++ b/riscv/picorv32/picosoc/ice40up5k_spram.v
diff --git a/picosoc/icebreaker.core b/riscv/picorv32/picosoc/icebreaker.core
index 5af5fd6..5af5fd6 100644
--- a/picosoc/icebreaker.core
+++ b/riscv/picorv32/picosoc/icebreaker.core
diff --git a/picosoc/icebreaker.pcf b/riscv/picorv32/picosoc/icebreaker.pcf
index 86cf78e..86cf78e 100644
--- a/picosoc/icebreaker.pcf
+++ b/riscv/picorv32/picosoc/icebreaker.pcf
diff --git a/picosoc/icebreaker.v b/riscv/picorv32/picosoc/icebreaker.v
index a943bc6..a943bc6 100644
--- a/picosoc/icebreaker.v
+++ b/riscv/picorv32/picosoc/icebreaker.v
diff --git a/picosoc/icebreaker_tb.v b/riscv/picorv32/picosoc/icebreaker_tb.v
index c09c10d..c09c10d 100644
--- a/picosoc/icebreaker_tb.v
+++ b/riscv/picorv32/picosoc/icebreaker_tb.v
diff --git a/picosoc/overview.svg b/riscv/picorv32/picosoc/overview.svg
index 2335f76..2335f76 100644
--- a/picosoc/overview.svg
+++ b/riscv/picorv32/picosoc/overview.svg
diff --git a/picosoc/performance.png b/riscv/picorv32/picosoc/performance.png
index aac75b2..aac75b2 100644
--- a/picosoc/performance.png
+++ b/riscv/picorv32/picosoc/performance.png
diff --git a/picosoc/performance.py b/riscv/picorv32/picosoc/performance.py
index 92c50c5..92c50c5 100644
--- a/picosoc/performance.py
+++ b/riscv/picorv32/picosoc/performance.py
diff --git a/picosoc/picosoc.core b/riscv/picorv32/picosoc/picosoc.core
index eb0988a..eb0988a 100644
--- a/picosoc/picosoc.core
+++ b/riscv/picorv32/picosoc/picosoc.core
diff --git a/picosoc/picosoc.v b/riscv/picorv32/picosoc/picosoc.v
index 9790791..9790791 100644
--- a/picosoc/picosoc.v
+++ b/riscv/picorv32/picosoc/picosoc.v
diff --git a/picosoc/sections.lds b/riscv/picorv32/picosoc/sections.lds
index f38d813..f38d813 100644
--- a/picosoc/sections.lds
+++ b/riscv/picorv32/picosoc/sections.lds
diff --git a/picosoc/simpleuart.v b/riscv/picorv32/picosoc/simpleuart.v
index 5ffef77..5ffef77 100644
--- a/picosoc/simpleuart.v
+++ b/riscv/picorv32/picosoc/simpleuart.v
diff --git a/picosoc/spiflash.core b/riscv/picorv32/picosoc/spiflash.core
index 1b7d153..1b7d153 100644
--- a/picosoc/spiflash.core
+++ b/riscv/picorv32/picosoc/spiflash.core
diff --git a/picosoc/spiflash.v b/riscv/picorv32/picosoc/spiflash.v
index 22b337b..22b337b 100644
--- a/picosoc/spiflash.v
+++ b/riscv/picorv32/picosoc/spiflash.v
diff --git a/picosoc/spiflash_tb.v b/riscv/picorv32/picosoc/spiflash_tb.v
index a5b5edc..a5b5edc 100644
--- a/picosoc/spiflash_tb.v
+++ b/riscv/picorv32/picosoc/spiflash_tb.v
diff --git a/picosoc/spimemio.v b/riscv/picorv32/picosoc/spimemio.v
index b4ee446..b4ee446 100644
--- a/picosoc/spimemio.v
+++ b/riscv/picorv32/picosoc/spimemio.v
diff --git a/picosoc/start.s b/riscv/picorv32/picosoc/start.s
index e9e18db..e9e18db 100644
--- a/picosoc/start.s
+++ b/riscv/picorv32/picosoc/start.s
diff --git a/scripts/csmith/.gitignore b/riscv/picorv32/scripts/csmith/.gitignore
index efd00f7..efd00f7 100644
--- a/scripts/csmith/.gitignore
+++ b/riscv/picorv32/scripts/csmith/.gitignore
diff --git a/scripts/csmith/Makefile b/riscv/picorv32/scripts/csmith/Makefile
index fd5107f..fd5107f 100644
--- a/scripts/csmith/Makefile
+++ b/riscv/picorv32/scripts/csmith/Makefile
diff --git a/scripts/csmith/riscv-isa-sim.diff b/riscv/picorv32/scripts/csmith/riscv-isa-sim.diff
index fd22280..fd22280 100644
--- a/scripts/csmith/riscv-isa-sim.diff
+++ b/riscv/picorv32/scripts/csmith/riscv-isa-sim.diff
diff --git a/scripts/csmith/start.S b/riscv/picorv32/scripts/csmith/start.S
index d8f110e..d8f110e 100644
--- a/scripts/csmith/start.S
+++ b/riscv/picorv32/scripts/csmith/start.S
diff --git a/scripts/csmith/syscalls.c b/riscv/picorv32/scripts/csmith/syscalls.c
index 8ea84ca..8ea84ca 100644
--- a/scripts/csmith/syscalls.c
+++ b/riscv/picorv32/scripts/csmith/syscalls.c
diff --git a/scripts/csmith/testbench.cc b/riscv/picorv32/scripts/csmith/testbench.cc
index 2925d0b..2925d0b 100644
--- a/scripts/csmith/testbench.cc
+++ b/riscv/picorv32/scripts/csmith/testbench.cc
diff --git a/scripts/csmith/testbench.v b/riscv/picorv32/scripts/csmith/testbench.v
index 9d9d8f6..9d9d8f6 100644
--- a/scripts/csmith/testbench.v
+++ b/riscv/picorv32/scripts/csmith/testbench.v
diff --git a/scripts/cxxdemo/.gitignore b/riscv/picorv32/scripts/cxxdemo/.gitignore
index 47e6b5c..47e6b5c 100644
--- a/scripts/cxxdemo/.gitignore
+++ b/riscv/picorv32/scripts/cxxdemo/.gitignore
diff --git a/scripts/cxxdemo/Makefile b/riscv/picorv32/scripts/cxxdemo/Makefile
index 2d95019..2d95019 100644
--- a/scripts/cxxdemo/Makefile
+++ b/riscv/picorv32/scripts/cxxdemo/Makefile
diff --git a/scripts/cxxdemo/firmware.cc b/riscv/picorv32/scripts/cxxdemo/firmware.cc
index 638c0dd..638c0dd 100644
--- a/scripts/cxxdemo/firmware.cc
+++ b/riscv/picorv32/scripts/cxxdemo/firmware.cc
diff --git a/scripts/cxxdemo/hex8tohex32.py b/riscv/picorv32/scripts/cxxdemo/hex8tohex32.py
index ae44101..ae44101 100644
--- a/scripts/cxxdemo/hex8tohex32.py
+++ b/riscv/picorv32/scripts/cxxdemo/hex8tohex32.py
diff --git a/scripts/cxxdemo/start.S b/riscv/picorv32/scripts/cxxdemo/start.S
index f872a14..f872a14 100644
--- a/scripts/cxxdemo/start.S
+++ b/riscv/picorv32/scripts/cxxdemo/start.S
diff --git a/scripts/cxxdemo/start.ld b/riscv/picorv32/scripts/cxxdemo/start.ld
index 773eee2..773eee2 100644
--- a/scripts/cxxdemo/start.ld
+++ b/riscv/picorv32/scripts/cxxdemo/start.ld
diff --git a/scripts/cxxdemo/syscalls.c b/riscv/picorv32/scripts/cxxdemo/syscalls.c
index 8ea84ca..8ea84ca 100644
--- a/scripts/cxxdemo/syscalls.c
+++ b/riscv/picorv32/scripts/cxxdemo/syscalls.c
diff --git a/scripts/cxxdemo/testbench.v b/riscv/picorv32/scripts/cxxdemo/testbench.v
index ac9af70..ac9af70 100644
--- a/scripts/cxxdemo/testbench.v
+++ b/riscv/picorv32/scripts/cxxdemo/testbench.v
diff --git a/scripts/icestorm/.gitignore b/riscv/picorv32/scripts/icestorm/.gitignore
index 9502e6b..9502e6b 100644
--- a/scripts/icestorm/.gitignore
+++ b/riscv/picorv32/scripts/icestorm/.gitignore
diff --git a/scripts/icestorm/Makefile b/riscv/picorv32/scripts/icestorm/Makefile
index 7672b41..7672b41 100644
--- a/scripts/icestorm/Makefile
+++ b/riscv/picorv32/scripts/icestorm/Makefile
diff --git a/scripts/icestorm/example.pcf b/riscv/picorv32/scripts/icestorm/example.pcf
index a5c7398..a5c7398 100644
--- a/scripts/icestorm/example.pcf
+++ b/riscv/picorv32/scripts/icestorm/example.pcf
diff --git a/scripts/icestorm/example.v b/riscv/picorv32/scripts/icestorm/example.v
index e1c64b4..e1c64b4 100644
--- a/scripts/icestorm/example.v
+++ b/riscv/picorv32/scripts/icestorm/example.v
diff --git a/scripts/icestorm/example_tb.v b/riscv/picorv32/scripts/icestorm/example_tb.v
index f04f8f8..f04f8f8 100644
--- a/scripts/icestorm/example_tb.v
+++ b/riscv/picorv32/scripts/icestorm/example_tb.v
diff --git a/riscv/picorv32/scripts/icestorm/firmware.S b/riscv/picorv32/scripts/icestorm/firmware.S
new file mode 100644
index 0000000..d19783d
--- /dev/null
+++ b/riscv/picorv32/scripts/icestorm/firmware.S
@@ -0,0 +1,12 @@
+.section .init
+.global main
+
+/* set stack pointer */
+lui sp, %hi(512)
+addi sp, sp, %lo(512)
+
+/* call main */
+jal ra, main
+
+/* break */
+ebreak
diff --git a/scripts/icestorm/firmware.c b/riscv/picorv32/scripts/icestorm/firmware.c
index 80a4661..80a4661 100644
--- a/scripts/icestorm/firmware.c
+++ b/riscv/picorv32/scripts/icestorm/firmware.c
diff --git a/scripts/presyn/firmware.lds b/riscv/picorv32/scripts/icestorm/firmware.lds
index 970000a..970000a 100644
--- a/scripts/presyn/firmware.lds
+++ b/riscv/picorv32/scripts/icestorm/firmware.lds
diff --git a/scripts/icestorm/readme.md b/riscv/picorv32/scripts/icestorm/readme.md
index 101391f..101391f 100644
--- a/scripts/icestorm/readme.md
+++ b/riscv/picorv32/scripts/icestorm/readme.md
diff --git a/scripts/presyn/.gitignore b/riscv/picorv32/scripts/presyn/.gitignore
index 4281b17..4281b17 100644
--- a/scripts/presyn/.gitignore
+++ b/riscv/picorv32/scripts/presyn/.gitignore
diff --git a/scripts/presyn/Makefile b/riscv/picorv32/scripts/presyn/Makefile
index d1c367e..d1c367e 100644
--- a/scripts/presyn/Makefile
+++ b/riscv/picorv32/scripts/presyn/Makefile
diff --git a/scripts/presyn/README b/riscv/picorv32/scripts/presyn/README
index 14aea33..14aea33 100644
--- a/scripts/presyn/README
+++ b/riscv/picorv32/scripts/presyn/README
diff --git a/scripts/presyn/firmware.S b/riscv/picorv32/scripts/presyn/firmware.S
index ec5caaa..ec5caaa 100644
--- a/scripts/presyn/firmware.S
+++ b/riscv/picorv32/scripts/presyn/firmware.S
diff --git a/scripts/presyn/firmware.c b/riscv/picorv32/scripts/presyn/firmware.c
index 6c62169..6c62169 100644
--- a/scripts/presyn/firmware.c
+++ b/riscv/picorv32/scripts/presyn/firmware.c
diff --git a/scripts/quartus/firmware.lds b/riscv/picorv32/scripts/presyn/firmware.lds
index 970000a..970000a 100644
--- a/scripts/quartus/firmware.lds
+++ b/riscv/picorv32/scripts/presyn/firmware.lds
diff --git a/scripts/presyn/picorv32_presyn.ys b/riscv/picorv32/scripts/presyn/picorv32_presyn.ys
index 5855a21..5855a21 100644
--- a/scripts/presyn/picorv32_presyn.ys
+++ b/riscv/picorv32/scripts/presyn/picorv32_presyn.ys
diff --git a/scripts/presyn/picorv32_regs.txt b/riscv/picorv32/scripts/presyn/picorv32_regs.txt
index 1cfbbeb..1cfbbeb 100644
--- a/scripts/presyn/picorv32_regs.txt
+++ b/riscv/picorv32/scripts/presyn/picorv32_regs.txt
diff --git a/scripts/presyn/testbench.v b/riscv/picorv32/scripts/presyn/testbench.v
index 59ff66b..59ff66b 100644
--- a/scripts/presyn/testbench.v
+++ b/riscv/picorv32/scripts/presyn/testbench.v
diff --git a/scripts/quartus/.gitignore b/riscv/picorv32/scripts/quartus/.gitignore
index d37ca0a..d37ca0a 100644
--- a/scripts/quartus/.gitignore
+++ b/riscv/picorv32/scripts/quartus/.gitignore
diff --git a/scripts/quartus/Makefile b/riscv/picorv32/scripts/quartus/Makefile
index c644609..c644609 100644
--- a/scripts/quartus/Makefile
+++ b/riscv/picorv32/scripts/quartus/Makefile
diff --git a/scripts/quartus/firmware.S b/riscv/picorv32/scripts/quartus/firmware.S
index c55a3ba..c55a3ba 100644
--- a/scripts/quartus/firmware.S
+++ b/riscv/picorv32/scripts/quartus/firmware.S
diff --git a/scripts/quartus/firmware.c b/riscv/picorv32/scripts/quartus/firmware.c
index 6c62169..6c62169 100644
--- a/scripts/quartus/firmware.c
+++ b/riscv/picorv32/scripts/quartus/firmware.c
diff --git a/scripts/vivado/firmware.lds b/riscv/picorv32/scripts/quartus/firmware.lds
index 970000a..970000a 100644
--- a/scripts/vivado/firmware.lds
+++ b/riscv/picorv32/scripts/quartus/firmware.lds
diff --git a/scripts/quartus/synth_area.sdc b/riscv/picorv32/scripts/quartus/synth_area.sdc
index 3c3d5a1..3c3d5a1 100644
--- a/scripts/quartus/synth_area.sdc
+++ b/riscv/picorv32/scripts/quartus/synth_area.sdc
diff --git a/scripts/quartus/synth_area_large.qsf b/riscv/picorv32/scripts/quartus/synth_area_large.qsf
index c09700b..c09700b 100644
--- a/scripts/quartus/synth_area_large.qsf
+++ b/riscv/picorv32/scripts/quartus/synth_area_large.qsf
diff --git a/scripts/quartus/synth_area_regular.qsf b/riscv/picorv32/scripts/quartus/synth_area_regular.qsf
index 8507413..8507413 100644
--- a/scripts/quartus/synth_area_regular.qsf
+++ b/riscv/picorv32/scripts/quartus/synth_area_regular.qsf
diff --git a/scripts/quartus/synth_area_small.qsf b/riscv/picorv32/scripts/quartus/synth_area_small.qsf
index 048ff96..048ff96 100644
--- a/scripts/quartus/synth_area_small.qsf
+++ b/riscv/picorv32/scripts/quartus/synth_area_small.qsf
diff --git a/scripts/quartus/synth_area_top.v b/riscv/picorv32/scripts/quartus/synth_area_top.v
index 6298a86..6298a86 100644
--- a/scripts/quartus/synth_area_top.v
+++ b/riscv/picorv32/scripts/quartus/synth_area_top.v
diff --git a/scripts/quartus/synth_speed.qsf b/riscv/picorv32/scripts/quartus/synth_speed.qsf
index 64490d4..64490d4 100644
--- a/scripts/quartus/synth_speed.qsf
+++ b/riscv/picorv32/scripts/quartus/synth_speed.qsf
diff --git a/scripts/quartus/synth_speed.sdc b/riscv/picorv32/scripts/quartus/synth_speed.sdc
index fef5704..fef5704 100644
--- a/scripts/quartus/synth_speed.sdc
+++ b/riscv/picorv32/scripts/quartus/synth_speed.sdc
diff --git a/scripts/quartus/synth_system.qsf b/riscv/picorv32/scripts/quartus/synth_system.qsf
index 1a84293..1a84293 100644
--- a/scripts/quartus/synth_system.qsf
+++ b/riscv/picorv32/scripts/quartus/synth_system.qsf
diff --git a/scripts/quartus/synth_system.sdc b/riscv/picorv32/scripts/quartus/synth_system.sdc
index 90ee3a2..90ee3a2 100644
--- a/scripts/quartus/synth_system.sdc
+++ b/riscv/picorv32/scripts/quartus/synth_system.sdc
diff --git a/scripts/quartus/synth_system.tcl b/riscv/picorv32/scripts/quartus/synth_system.tcl
index 26ea01c..26ea01c 100644
--- a/scripts/quartus/synth_system.tcl
+++ b/riscv/picorv32/scripts/quartus/synth_system.tcl
diff --git a/scripts/quartus/system.v b/riscv/picorv32/scripts/quartus/system.v
index 19a4b8d..19a4b8d 100644
--- a/scripts/quartus/system.v
+++ b/riscv/picorv32/scripts/quartus/system.v
diff --git a/scripts/quartus/system_tb.v b/riscv/picorv32/scripts/quartus/system_tb.v
index a66d612..a66d612 100644
--- a/scripts/quartus/system_tb.v
+++ b/riscv/picorv32/scripts/quartus/system_tb.v
diff --git a/scripts/quartus/table.sh b/riscv/picorv32/scripts/quartus/table.sh
index f5e6efe..f5e6efe 100644
--- a/scripts/quartus/table.sh
+++ b/riscv/picorv32/scripts/quartus/table.sh
diff --git a/scripts/quartus/tabtest.sh b/riscv/picorv32/scripts/quartus/tabtest.sh
index 2fd1b40..2fd1b40 100644
--- a/scripts/quartus/tabtest.sh
+++ b/riscv/picorv32/scripts/quartus/tabtest.sh
diff --git a/scripts/quartus/tabtest.v b/riscv/picorv32/scripts/quartus/tabtest.v
index cdf2057..cdf2057 100644
--- a/scripts/quartus/tabtest.v
+++ b/riscv/picorv32/scripts/quartus/tabtest.v
diff --git a/scripts/romload/.gitignore b/riscv/picorv32/scripts/romload/.gitignore
index 6f1295b..6f1295b 100644
--- a/scripts/romload/.gitignore
+++ b/riscv/picorv32/scripts/romload/.gitignore
diff --git a/scripts/romload/Makefile b/riscv/picorv32/scripts/romload/Makefile
index d510fa8..d510fa8 100644
--- a/scripts/romload/Makefile
+++ b/riscv/picorv32/scripts/romload/Makefile
diff --git a/scripts/romload/firmware.c b/riscv/picorv32/scripts/romload/firmware.c
index 4bc9ed8..4bc9ed8 100644
--- a/scripts/romload/firmware.c
+++ b/riscv/picorv32/scripts/romload/firmware.c
diff --git a/scripts/romload/hex8tohex32.py b/riscv/picorv32/scripts/romload/hex8tohex32.py
index ae44101..ae44101 100644
--- a/scripts/romload/hex8tohex32.py
+++ b/riscv/picorv32/scripts/romload/hex8tohex32.py
diff --git a/scripts/romload/map2debug.py b/riscv/picorv32/scripts/romload/map2debug.py
index fc5c97c..fc5c97c 100644
--- a/scripts/romload/map2debug.py
+++ b/riscv/picorv32/scripts/romload/map2debug.py
diff --git a/scripts/romload/sections.ld b/riscv/picorv32/scripts/romload/sections.ld
index 2ec3954..2ec3954 100644
--- a/scripts/romload/sections.ld
+++ b/riscv/picorv32/scripts/romload/sections.ld
diff --git a/scripts/romload/start.S b/riscv/picorv32/scripts/romload/start.S
index be59808..be59808 100644
--- a/scripts/romload/start.S
+++ b/riscv/picorv32/scripts/romload/start.S
diff --git a/scripts/romload/syscalls.c b/riscv/picorv32/scripts/romload/syscalls.c
index 8ea84ca..8ea84ca 100644
--- a/scripts/romload/syscalls.c
+++ b/riscv/picorv32/scripts/romload/syscalls.c
diff --git a/scripts/romload/testbench.v b/riscv/picorv32/scripts/romload/testbench.v
index e38819d..e38819d 100644
--- a/scripts/romload/testbench.v
+++ b/riscv/picorv32/scripts/romload/testbench.v
diff --git a/scripts/smtbmc/.gitignore b/riscv/picorv32/scripts/smtbmc/.gitignore
index 1ce906e..1ce906e 100644
--- a/scripts/smtbmc/.gitignore
+++ b/riscv/picorv32/scripts/smtbmc/.gitignore
diff --git a/scripts/smtbmc/axicheck.sh b/riscv/picorv32/scripts/smtbmc/axicheck.sh
index 732b3b8..732b3b8 100644
--- a/scripts/smtbmc/axicheck.sh
+++ b/riscv/picorv32/scripts/smtbmc/axicheck.sh
diff --git a/scripts/smtbmc/axicheck.v b/riscv/picorv32/scripts/smtbmc/axicheck.v
index 80eda48..80eda48 100644
--- a/scripts/smtbmc/axicheck.v
+++ b/riscv/picorv32/scripts/smtbmc/axicheck.v
diff --git a/scripts/smtbmc/axicheck2.sh b/riscv/picorv32/scripts/smtbmc/axicheck2.sh
index df20855..df20855 100644
--- a/scripts/smtbmc/axicheck2.sh
+++ b/riscv/picorv32/scripts/smtbmc/axicheck2.sh
diff --git a/scripts/smtbmc/axicheck2.smtc b/riscv/picorv32/scripts/smtbmc/axicheck2.smtc
index 1f8c5ea..1f8c5ea 100644
--- a/scripts/smtbmc/axicheck2.smtc
+++ b/riscv/picorv32/scripts/smtbmc/axicheck2.smtc
diff --git a/scripts/smtbmc/axicheck2.v b/riscv/picorv32/scripts/smtbmc/axicheck2.v
index 3d24a2e..3d24a2e 100644
--- a/scripts/smtbmc/axicheck2.v
+++ b/riscv/picorv32/scripts/smtbmc/axicheck2.v
diff --git a/scripts/smtbmc/mulcmp.sh b/riscv/picorv32/scripts/smtbmc/mulcmp.sh
index 586d72a..586d72a 100644
--- a/scripts/smtbmc/mulcmp.sh
+++ b/riscv/picorv32/scripts/smtbmc/mulcmp.sh
diff --git a/scripts/smtbmc/mulcmp.v b/riscv/picorv32/scripts/smtbmc/mulcmp.v
index 20c47f3..20c47f3 100644
--- a/scripts/smtbmc/mulcmp.v
+++ b/riscv/picorv32/scripts/smtbmc/mulcmp.v
diff --git a/scripts/smtbmc/notrap_validop.sh b/riscv/picorv32/scripts/smtbmc/notrap_validop.sh
index 95e0f92..95e0f92 100644
--- a/scripts/smtbmc/notrap_validop.sh
+++ b/riscv/picorv32/scripts/smtbmc/notrap_validop.sh
diff --git a/scripts/smtbmc/notrap_validop.v b/riscv/picorv32/scripts/smtbmc/notrap_validop.v
index 8e50304..8e50304 100644
--- a/scripts/smtbmc/notrap_validop.v
+++ b/riscv/picorv32/scripts/smtbmc/notrap_validop.v
diff --git a/scripts/smtbmc/opcode.v b/riscv/picorv32/scripts/smtbmc/opcode.v
index 7a13bd2..7a13bd2 100644
--- a/scripts/smtbmc/opcode.v
+++ b/riscv/picorv32/scripts/smtbmc/opcode.v
diff --git a/scripts/smtbmc/tracecmp.gtkw b/riscv/picorv32/scripts/smtbmc/tracecmp.gtkw
index 09dd9b2..09dd9b2 100644
--- a/scripts/smtbmc/tracecmp.gtkw
+++ b/riscv/picorv32/scripts/smtbmc/tracecmp.gtkw
diff --git a/scripts/smtbmc/tracecmp.sh b/riscv/picorv32/scripts/smtbmc/tracecmp.sh
index 449af52..449af52 100644
--- a/scripts/smtbmc/tracecmp.sh
+++ b/riscv/picorv32/scripts/smtbmc/tracecmp.sh
diff --git a/scripts/smtbmc/tracecmp.smtc b/riscv/picorv32/scripts/smtbmc/tracecmp.smtc
index 477c7d0..477c7d0 100644
--- a/scripts/smtbmc/tracecmp.smtc
+++ b/riscv/picorv32/scripts/smtbmc/tracecmp.smtc
diff --git a/scripts/smtbmc/tracecmp.v b/riscv/picorv32/scripts/smtbmc/tracecmp.v
index 8ac4157..8ac4157 100644
--- a/scripts/smtbmc/tracecmp.v
+++ b/riscv/picorv32/scripts/smtbmc/tracecmp.v
diff --git a/scripts/smtbmc/tracecmp2.sh b/riscv/picorv32/scripts/smtbmc/tracecmp2.sh
index ddaf285..ddaf285 100644
--- a/scripts/smtbmc/tracecmp2.sh
+++ b/riscv/picorv32/scripts/smtbmc/tracecmp2.sh
diff --git a/scripts/smtbmc/tracecmp2.smtc b/riscv/picorv32/scripts/smtbmc/tracecmp2.smtc
index 3b7fd0a..3b7fd0a 100644
--- a/scripts/smtbmc/tracecmp2.smtc
+++ b/riscv/picorv32/scripts/smtbmc/tracecmp2.smtc
diff --git a/scripts/smtbmc/tracecmp2.v b/riscv/picorv32/scripts/smtbmc/tracecmp2.v
index 42f39a9..42f39a9 100644
--- a/scripts/smtbmc/tracecmp2.v
+++ b/riscv/picorv32/scripts/smtbmc/tracecmp2.v
diff --git a/scripts/smtbmc/tracecmp3.sh b/riscv/picorv32/scripts/smtbmc/tracecmp3.sh
index bfa0b3c..bfa0b3c 100644
--- a/scripts/smtbmc/tracecmp3.sh
+++ b/riscv/picorv32/scripts/smtbmc/tracecmp3.sh
diff --git a/scripts/smtbmc/tracecmp3.v b/riscv/picorv32/scripts/smtbmc/tracecmp3.v
index a1bb63b..a1bb63b 100644
--- a/scripts/smtbmc/tracecmp3.v
+++ b/riscv/picorv32/scripts/smtbmc/tracecmp3.v
diff --git a/scripts/tomthumbtg/.gitignore b/riscv/picorv32/scripts/tomthumbtg/.gitignore
index c1e6b04..c1e6b04 100644
--- a/scripts/tomthumbtg/.gitignore
+++ b/riscv/picorv32/scripts/tomthumbtg/.gitignore
diff --git a/scripts/tomthumbtg/README b/riscv/picorv32/scripts/tomthumbtg/README
index 4e12ba8..4e12ba8 100644
--- a/scripts/tomthumbtg/README
+++ b/riscv/picorv32/scripts/tomthumbtg/README
diff --git a/scripts/tomthumbtg/run.sh b/riscv/picorv32/scripts/tomthumbtg/run.sh
index 63a6935..63a6935 100644
--- a/scripts/tomthumbtg/run.sh
+++ b/riscv/picorv32/scripts/tomthumbtg/run.sh
diff --git a/scripts/tomthumbtg/sections.lds b/riscv/picorv32/scripts/tomthumbtg/sections.lds
index 8962f5c..8962f5c 100644
--- a/scripts/tomthumbtg/sections.lds
+++ b/riscv/picorv32/scripts/tomthumbtg/sections.lds
diff --git a/scripts/tomthumbtg/start.S b/riscv/picorv32/scripts/tomthumbtg/start.S
index 541c8a4..541c8a4 100644
--- a/scripts/tomthumbtg/start.S
+++ b/riscv/picorv32/scripts/tomthumbtg/start.S
diff --git a/scripts/tomthumbtg/testbench.v b/riscv/picorv32/scripts/tomthumbtg/testbench.v
index c39ebca..c39ebca 100644
--- a/scripts/tomthumbtg/testbench.v
+++ b/riscv/picorv32/scripts/tomthumbtg/testbench.v
diff --git a/scripts/torture/.gitignore b/riscv/picorv32/scripts/torture/.gitignore
index b58f70b..b58f70b 100644
--- a/scripts/torture/.gitignore
+++ b/riscv/picorv32/scripts/torture/.gitignore
diff --git a/scripts/torture/Makefile b/riscv/picorv32/scripts/torture/Makefile
index 4dd075c..4dd075c 100644
--- a/scripts/torture/Makefile
+++ b/riscv/picorv32/scripts/torture/Makefile
diff --git a/scripts/torture/README b/riscv/picorv32/scripts/torture/README
index d62671d..d62671d 100644
--- a/scripts/torture/README
+++ b/riscv/picorv32/scripts/torture/README
diff --git a/scripts/torture/asmcheck.py b/riscv/picorv32/scripts/torture/asmcheck.py
index 8a22c67..8a22c67 100644
--- a/scripts/torture/asmcheck.py
+++ b/riscv/picorv32/scripts/torture/asmcheck.py
diff --git a/scripts/torture/config.py b/riscv/picorv32/scripts/torture/config.py
index 478f046..478f046 100644
--- a/scripts/torture/config.py
+++ b/riscv/picorv32/scripts/torture/config.py
diff --git a/scripts/torture/riscv-isa-sim-notrap.diff b/riscv/picorv32/scripts/torture/riscv-isa-sim-notrap.diff
index df7c059..df7c059 100644
--- a/scripts/torture/riscv-isa-sim-notrap.diff
+++ b/riscv/picorv32/scripts/torture/riscv-isa-sim-notrap.diff
diff --git a/scripts/torture/riscv-isa-sim-sbreak.diff b/riscv/picorv32/scripts/torture/riscv-isa-sim-sbreak.diff
index 9728fc8..9728fc8 100644
--- a/scripts/torture/riscv-isa-sim-sbreak.diff
+++ b/riscv/picorv32/scripts/torture/riscv-isa-sim-sbreak.diff
diff --git a/scripts/torture/riscv-torture-genloop.diff b/riscv/picorv32/scripts/torture/riscv-torture-genloop.diff
index a0a2fd1..a0a2fd1 100644
--- a/scripts/torture/riscv-torture-genloop.diff
+++ b/riscv/picorv32/scripts/torture/riscv-torture-genloop.diff
diff --git a/scripts/torture/riscv-torture-rv32.diff b/riscv/picorv32/scripts/torture/riscv-torture-rv32.diff
index fef49b3..fef49b3 100644
--- a/scripts/torture/riscv-torture-rv32.diff
+++ b/riscv/picorv32/scripts/torture/riscv-torture-rv32.diff
diff --git a/scripts/torture/riscv_test.h b/riscv/picorv32/scripts/torture/riscv_test.h
index 36c5b54..36c5b54 100644
--- a/scripts/torture/riscv_test.h
+++ b/riscv/picorv32/scripts/torture/riscv_test.h
diff --git a/scripts/torture/sections.lds b/riscv/picorv32/scripts/torture/sections.lds
index a9487e2..a9487e2 100644
--- a/scripts/torture/sections.lds
+++ b/riscv/picorv32/scripts/torture/sections.lds
diff --git a/scripts/torture/test.sh b/riscv/picorv32/scripts/torture/test.sh
index 17c5a7c..17c5a7c 100644
--- a/scripts/torture/test.sh
+++ b/riscv/picorv32/scripts/torture/test.sh
diff --git a/scripts/torture/testbench.cc b/riscv/picorv32/scripts/torture/testbench.cc
index 2925d0b..2925d0b 100644
--- a/scripts/torture/testbench.cc
+++ b/riscv/picorv32/scripts/torture/testbench.cc
diff --git a/scripts/torture/testbench.v b/riscv/picorv32/scripts/torture/testbench.v
index 326de0e..326de0e 100644
--- a/scripts/torture/testbench.v
+++ b/riscv/picorv32/scripts/torture/testbench.v
diff --git a/scripts/vivado/.gitignore b/riscv/picorv32/scripts/vivado/.gitignore
index 2374269..2374269 100644
--- a/scripts/vivado/.gitignore
+++ b/riscv/picorv32/scripts/vivado/.gitignore
diff --git a/scripts/vivado/Makefile b/riscv/picorv32/scripts/vivado/Makefile
index 3c92901..3c92901 100644
--- a/scripts/vivado/Makefile
+++ b/riscv/picorv32/scripts/vivado/Makefile
diff --git a/scripts/vivado/firmware.S b/riscv/picorv32/scripts/vivado/firmware.S
index c55a3ba..c55a3ba 100644
--- a/scripts/vivado/firmware.S
+++ b/riscv/picorv32/scripts/vivado/firmware.S
diff --git a/scripts/vivado/firmware.c b/riscv/picorv32/scripts/vivado/firmware.c
index 6c62169..6c62169 100644
--- a/scripts/vivado/firmware.c
+++ b/riscv/picorv32/scripts/vivado/firmware.c
diff --git a/riscv/picorv32/scripts/vivado/firmware.lds b/riscv/picorv32/scripts/vivado/firmware.lds
new file mode 100644
index 0000000..970000a
--- /dev/null
+++ b/riscv/picorv32/scripts/vivado/firmware.lds
@@ -0,0 +1,11 @@
+SECTIONS {
+	.memory : {
+		. = 0x000000;
+		*(.init);
+		*(.text);
+		*(*);
+		. = ALIGN(4);
+		end = .;
+	}
+}
+
diff --git a/scripts/vivado/synth_area.tcl b/riscv/picorv32/scripts/vivado/synth_area.tcl
index c222a00..c222a00 100644
--- a/scripts/vivado/synth_area.tcl
+++ b/riscv/picorv32/scripts/vivado/synth_area.tcl
diff --git a/scripts/vivado/synth_area.xdc b/riscv/picorv32/scripts/vivado/synth_area.xdc
index 3c3d5a1..3c3d5a1 100644
--- a/scripts/vivado/synth_area.xdc
+++ b/riscv/picorv32/scripts/vivado/synth_area.xdc
diff --git a/scripts/vivado/synth_area_large.tcl b/riscv/picorv32/scripts/vivado/synth_area_large.tcl
index af611b5..af611b5 100644
--- a/scripts/vivado/synth_area_large.tcl
+++ b/riscv/picorv32/scripts/vivado/synth_area_large.tcl
diff --git a/scripts/vivado/synth_area_regular.tcl b/riscv/picorv32/scripts/vivado/synth_area_regular.tcl
index 2bf6b4c..2bf6b4c 100644
--- a/scripts/vivado/synth_area_regular.tcl
+++ b/riscv/picorv32/scripts/vivado/synth_area_regular.tcl
diff --git a/scripts/vivado/synth_area_small.tcl b/riscv/picorv32/scripts/vivado/synth_area_small.tcl
index 11d2104..11d2104 100644
--- a/scripts/vivado/synth_area_small.tcl
+++ b/riscv/picorv32/scripts/vivado/synth_area_small.tcl
diff --git a/scripts/vivado/synth_area_top.v b/riscv/picorv32/scripts/vivado/synth_area_top.v
index 6298a86..6298a86 100644
--- a/scripts/vivado/synth_area_top.v
+++ b/riscv/picorv32/scripts/vivado/synth_area_top.v
diff --git a/scripts/vivado/synth_speed.tcl b/riscv/picorv32/scripts/vivado/synth_speed.tcl
index f3874e4..f3874e4 100644
--- a/scripts/vivado/synth_speed.tcl
+++ b/riscv/picorv32/scripts/vivado/synth_speed.tcl
diff --git a/scripts/vivado/synth_speed.xdc b/riscv/picorv32/scripts/vivado/synth_speed.xdc
index 877ec8d..877ec8d 100644
--- a/scripts/vivado/synth_speed.xdc
+++ b/riscv/picorv32/scripts/vivado/synth_speed.xdc
diff --git a/scripts/vivado/synth_system.tcl b/riscv/picorv32/scripts/vivado/synth_system.tcl
index 26ea01c..26ea01c 100644
--- a/scripts/vivado/synth_system.tcl
+++ b/riscv/picorv32/scripts/vivado/synth_system.tcl
diff --git a/scripts/vivado/synth_system.xdc b/riscv/picorv32/scripts/vivado/synth_system.xdc
index 5748466..5748466 100644
--- a/scripts/vivado/synth_system.xdc
+++ b/riscv/picorv32/scripts/vivado/synth_system.xdc
diff --git a/scripts/vivado/system.v b/riscv/picorv32/scripts/vivado/system.v
index c4882a1..c4882a1 100644
--- a/scripts/vivado/system.v
+++ b/riscv/picorv32/scripts/vivado/system.v
diff --git a/scripts/vivado/system_tb.v b/riscv/picorv32/scripts/vivado/system_tb.v
index a66d612..a66d612 100644
--- a/scripts/vivado/system_tb.v
+++ b/riscv/picorv32/scripts/vivado/system_tb.v
diff --git a/scripts/vivado/table.sh b/riscv/picorv32/scripts/vivado/table.sh
index 81e2cf4..81e2cf4 100644
--- a/scripts/vivado/table.sh
+++ b/riscv/picorv32/scripts/vivado/table.sh
diff --git a/scripts/vivado/tabtest.sh b/riscv/picorv32/scripts/vivado/tabtest.sh
index bc3d840..bc3d840 100644
--- a/scripts/vivado/tabtest.sh
+++ b/riscv/picorv32/scripts/vivado/tabtest.sh
diff --git a/scripts/vivado/tabtest.v b/riscv/picorv32/scripts/vivado/tabtest.v
index cdf2057..cdf2057 100644
--- a/scripts/vivado/tabtest.v
+++ b/riscv/picorv32/scripts/vivado/tabtest.v
diff --git a/scripts/yosys-cmp/README.md b/riscv/picorv32/scripts/yosys-cmp/README.md
index acb2c6c..acb2c6c 100644
--- a/scripts/yosys-cmp/README.md
+++ b/riscv/picorv32/scripts/yosys-cmp/README.md
diff --git a/scripts/yosys-cmp/lse.sh b/riscv/picorv32/scripts/yosys-cmp/lse.sh
index a802c67..a802c67 100644
--- a/scripts/yosys-cmp/lse.sh
+++ b/riscv/picorv32/scripts/yosys-cmp/lse.sh
diff --git a/scripts/yosys-cmp/synplify.sh b/riscv/picorv32/scripts/yosys-cmp/synplify.sh
index d0a2a08..d0a2a08 100644
--- a/scripts/yosys-cmp/synplify.sh
+++ b/riscv/picorv32/scripts/yosys-cmp/synplify.sh
diff --git a/scripts/yosys-cmp/vivado.tcl b/riscv/picorv32/scripts/yosys-cmp/vivado.tcl
index 560b880..560b880 100644
--- a/scripts/yosys-cmp/vivado.tcl
+++ b/riscv/picorv32/scripts/yosys-cmp/vivado.tcl
diff --git a/scripts/yosys-cmp/yosys_ice40.ys b/riscv/picorv32/scripts/yosys-cmp/yosys_ice40.ys
index b14b338..b14b338 100644
--- a/scripts/yosys-cmp/yosys_ice40.ys
+++ b/riscv/picorv32/scripts/yosys-cmp/yosys_ice40.ys
diff --git a/scripts/yosys-cmp/yosys_xilinx.ys b/riscv/picorv32/scripts/yosys-cmp/yosys_xilinx.ys
index ead52a4..ead52a4 100644
--- a/scripts/yosys-cmp/yosys_xilinx.ys
+++ b/riscv/picorv32/scripts/yosys-cmp/yosys_xilinx.ys
diff --git a/scripts/yosys/.gitignore b/riscv/picorv32/scripts/yosys/.gitignore
index d6fc3e3..d6fc3e3 100644
--- a/scripts/yosys/.gitignore
+++ b/riscv/picorv32/scripts/yosys/.gitignore
diff --git a/scripts/yosys/synth_gates.lib b/riscv/picorv32/scripts/yosys/synth_gates.lib
index be706dd..be706dd 100644
--- a/scripts/yosys/synth_gates.lib
+++ b/riscv/picorv32/scripts/yosys/synth_gates.lib
diff --git a/scripts/yosys/synth_gates.v b/riscv/picorv32/scripts/yosys/synth_gates.v
index 8e2504e..8e2504e 100644
--- a/scripts/yosys/synth_gates.v
+++ b/riscv/picorv32/scripts/yosys/synth_gates.v
diff --git a/scripts/yosys/synth_gates.ys b/riscv/picorv32/scripts/yosys/synth_gates.ys
index 311d767..311d767 100644
--- a/scripts/yosys/synth_gates.ys
+++ b/riscv/picorv32/scripts/yosys/synth_gates.ys
diff --git a/scripts/yosys/synth_osu018.sh b/riscv/picorv32/scripts/yosys/synth_osu018.sh
index 7a8693d..7a8693d 100644
--- a/scripts/yosys/synth_osu018.sh
+++ b/riscv/picorv32/scripts/yosys/synth_osu018.sh
diff --git a/scripts/yosys/synth_sim.ys b/riscv/picorv32/scripts/yosys/synth_sim.ys
index ded89d9..ded89d9 100644
--- a/scripts/yosys/synth_sim.ys
+++ b/riscv/picorv32/scripts/yosys/synth_sim.ys
diff --git a/shell.nix b/riscv/picorv32/shell.nix
index 92ec1ff..92ec1ff 100644
--- a/shell.nix
+++ b/riscv/picorv32/shell.nix
diff --git a/showtrace.py b/riscv/picorv32/showtrace.py
index a5d1021..a5d1021 100644
--- a/showtrace.py
+++ b/riscv/picorv32/showtrace.py
diff --git a/testbench.cc b/riscv/picorv32/testbench.cc
index 61c4366..61c4366 100644
--- a/testbench.cc
+++ b/riscv/picorv32/testbench.cc
diff --git a/testbench.v b/riscv/picorv32/testbench.v
index 9d8e249..9d8e249 100644
--- a/testbench.v
+++ b/riscv/picorv32/testbench.v
diff --git a/testbench_ez.v b/riscv/picorv32/testbench_ez.v
index 55c9c69..55c9c69 100644
--- a/testbench_ez.v
+++ b/riscv/picorv32/testbench_ez.v
diff --git a/testbench_wb.v b/riscv/picorv32/testbench_wb.v
index 4e1a8eb..4e1a8eb 100644
--- a/testbench_wb.v
+++ b/riscv/picorv32/testbench_wb.v
diff --git a/tests/LICENSE b/riscv/picorv32/tests/LICENSE
index 48fe522..48fe522 100644
--- a/tests/LICENSE
+++ b/riscv/picorv32/tests/LICENSE
diff --git a/tests/README b/riscv/picorv32/tests/README
index 3c1a912..3c1a912 100644
--- a/tests/README
+++ b/riscv/picorv32/tests/README
diff --git a/tests/add.S b/riscv/picorv32/tests/add.S
index 2eb330e..2eb330e 100644
--- a/tests/add.S
+++ b/riscv/picorv32/tests/add.S
diff --git a/tests/addi.S b/riscv/picorv32/tests/addi.S
index f7a418b..f7a418b 100644
--- a/tests/addi.S
+++ b/riscv/picorv32/tests/addi.S
diff --git a/tests/and.S b/riscv/picorv32/tests/and.S
index 561ae3b..561ae3b 100644
--- a/tests/and.S
+++ b/riscv/picorv32/tests/and.S
diff --git a/tests/andi.S b/riscv/picorv32/tests/andi.S
index c2ae94d..c2ae94d 100644
--- a/tests/andi.S
+++ b/riscv/picorv32/tests/andi.S
diff --git a/tests/auipc.S b/riscv/picorv32/tests/auipc.S
index c67e3c9..c67e3c9 100644
--- a/tests/auipc.S
+++ b/riscv/picorv32/tests/auipc.S
diff --git a/tests/beq.S b/riscv/picorv32/tests/beq.S
index c972eff..c972eff 100644
--- a/tests/beq.S
+++ b/riscv/picorv32/tests/beq.S
diff --git a/tests/bge.S b/riscv/picorv32/tests/bge.S
index d6aea7c..d6aea7c 100644
--- a/tests/bge.S
+++ b/riscv/picorv32/tests/bge.S
diff --git a/tests/bgeu.S b/riscv/picorv32/tests/bgeu.S
index 114c845..114c845 100644
--- a/tests/bgeu.S
+++ b/riscv/picorv32/tests/bgeu.S
diff --git a/tests/blt.S b/riscv/picorv32/tests/blt.S
index 12e28c3..12e28c3 100644
--- a/tests/blt.S
+++ b/riscv/picorv32/tests/blt.S
diff --git a/tests/bltu.S b/riscv/picorv32/tests/bltu.S
index 5dcfe7e..5dcfe7e 100644
--- a/tests/bltu.S
+++ b/riscv/picorv32/tests/bltu.S
diff --git a/tests/bne.S b/riscv/picorv32/tests/bne.S
index 0b33753..0b33753 100644
--- a/tests/bne.S
+++ b/riscv/picorv32/tests/bne.S
diff --git a/tests/div.S b/riscv/picorv32/tests/div.S
index 24dc9ff..24dc9ff 100644
--- a/tests/div.S
+++ b/riscv/picorv32/tests/div.S
diff --git a/tests/divu.S b/riscv/picorv32/tests/divu.S
index cd348c9..cd348c9 100644
--- a/tests/divu.S
+++ b/riscv/picorv32/tests/divu.S
diff --git a/tests/j.S b/riscv/picorv32/tests/j.S
index 259a236..259a236 100644
--- a/tests/j.S
+++ b/riscv/picorv32/tests/j.S
diff --git a/tests/jal.S b/riscv/picorv32/tests/jal.S
index 38a1c76..38a1c76 100644
--- a/tests/jal.S
+++ b/riscv/picorv32/tests/jal.S
diff --git a/tests/jalr.S b/riscv/picorv32/tests/jalr.S
index 52117ab..52117ab 100644
--- a/tests/jalr.S
+++ b/riscv/picorv32/tests/jalr.S
diff --git a/tests/lb.S b/riscv/picorv32/tests/lb.S
index eaf7902..eaf7902 100644
--- a/tests/lb.S
+++ b/riscv/picorv32/tests/lb.S
diff --git a/tests/lbu.S b/riscv/picorv32/tests/lbu.S
index 027b643..027b643 100644
--- a/tests/lbu.S
+++ b/riscv/picorv32/tests/lbu.S
diff --git a/tests/lh.S b/riscv/picorv32/tests/lh.S
index d8eda91..d8eda91 100644
--- a/tests/lh.S
+++ b/riscv/picorv32/tests/lh.S
diff --git a/tests/lhu.S b/riscv/picorv32/tests/lhu.S
index 71daec6..71daec6 100644
--- a/tests/lhu.S
+++ b/riscv/picorv32/tests/lhu.S
diff --git a/tests/lui.S b/riscv/picorv32/tests/lui.S
index 50822d1..50822d1 100644
--- a/tests/lui.S
+++ b/riscv/picorv32/tests/lui.S
diff --git a/tests/lw.S b/riscv/picorv32/tests/lw.S
index 4a07838..4a07838 100644
--- a/tests/lw.S
+++ b/riscv/picorv32/tests/lw.S
diff --git a/tests/mul.S b/riscv/picorv32/tests/mul.S
index 0368629..0368629 100644
--- a/tests/mul.S
+++ b/riscv/picorv32/tests/mul.S
diff --git a/tests/mulh.S b/riscv/picorv32/tests/mulh.S
index e583f5f..e583f5f 100644
--- a/tests/mulh.S
+++ b/riscv/picorv32/tests/mulh.S
diff --git a/tests/mulhsu.S b/riscv/picorv32/tests/mulhsu.S
index 28b3690..28b3690 100644
--- a/tests/mulhsu.S
+++ b/riscv/picorv32/tests/mulhsu.S
diff --git a/tests/mulhu.S b/riscv/picorv32/tests/mulhu.S
index 601dcff..601dcff 100644
--- a/tests/mulhu.S
+++ b/riscv/picorv32/tests/mulhu.S
diff --git a/tests/or.S b/riscv/picorv32/tests/or.S
index 110bcc4..110bcc4 100644
--- a/tests/or.S
+++ b/riscv/picorv32/tests/or.S
diff --git a/tests/ori.S b/riscv/picorv32/tests/ori.S
index a674784..a674784 100644
--- a/tests/ori.S
+++ b/riscv/picorv32/tests/ori.S
diff --git a/tests/rem.S b/riscv/picorv32/tests/rem.S
index 7955736..7955736 100644
--- a/tests/rem.S
+++ b/riscv/picorv32/tests/rem.S
diff --git a/tests/remu.S b/riscv/picorv32/tests/remu.S
index a96cfc1..a96cfc1 100644
--- a/tests/remu.S
+++ b/riscv/picorv32/tests/remu.S
diff --git a/tests/riscv_test.h b/riscv/picorv32/tests/riscv_test.h
index 71a4366..71a4366 100644
--- a/tests/riscv_test.h
+++ b/riscv/picorv32/tests/riscv_test.h
diff --git a/tests/sb.S b/riscv/picorv32/tests/sb.S
index 05d1894..05d1894 100644
--- a/tests/sb.S
+++ b/riscv/picorv32/tests/sb.S
diff --git a/tests/sh.S b/riscv/picorv32/tests/sh.S
index 387e181..387e181 100644
--- a/tests/sh.S
+++ b/riscv/picorv32/tests/sh.S
diff --git a/tests/simple.S b/riscv/picorv32/tests/simple.S
index 92cf203..92cf203 100644
--- a/tests/simple.S
+++ b/riscv/picorv32/tests/simple.S
diff --git a/tests/sll.S b/riscv/picorv32/tests/sll.S
index d297ac5..d297ac5 100644
--- a/tests/sll.S
+++ b/riscv/picorv32/tests/sll.S
diff --git a/tests/slli.S b/riscv/picorv32/tests/slli.S
index a51eec9..a51eec9 100644
--- a/tests/slli.S
+++ b/riscv/picorv32/tests/slli.S
diff --git a/tests/slt.S b/riscv/picorv32/tests/slt.S
index 3abf82b..3abf82b 100644
--- a/tests/slt.S
+++ b/riscv/picorv32/tests/slt.S
diff --git a/tests/slti.S b/riscv/picorv32/tests/slti.S
index 730cbe2..730cbe2 100644
--- a/tests/slti.S
+++ b/riscv/picorv32/tests/slti.S
diff --git a/tests/sra.S b/riscv/picorv32/tests/sra.S
index 8c1de36..8c1de36 100644
--- a/tests/sra.S
+++ b/riscv/picorv32/tests/sra.S
diff --git a/tests/srai.S b/riscv/picorv32/tests/srai.S
index 4638190..4638190 100644
--- a/tests/srai.S
+++ b/riscv/picorv32/tests/srai.S
diff --git a/tests/srl.S b/riscv/picorv32/tests/srl.S
index 35cc4c7..35cc4c7 100644
--- a/tests/srl.S
+++ b/riscv/picorv32/tests/srl.S
diff --git a/tests/srli.S b/riscv/picorv32/tests/srli.S
index be56dc3..be56dc3 100644
--- a/tests/srli.S
+++ b/riscv/picorv32/tests/srli.S
diff --git a/tests/sub.S b/riscv/picorv32/tests/sub.S
index ad56e3e..ad56e3e 100644
--- a/tests/sub.S
+++ b/riscv/picorv32/tests/sub.S
diff --git a/tests/sw.S b/riscv/picorv32/tests/sw.S
index fbf76cc..fbf76cc 100644
--- a/tests/sw.S
+++ b/riscv/picorv32/tests/sw.S
diff --git a/tests/test_macros.h b/riscv/picorv32/tests/test_macros.h
index 05ed7c8..05ed7c8 100644
--- a/tests/test_macros.h
+++ b/riscv/picorv32/tests/test_macros.h
diff --git a/tests/xor.S b/riscv/picorv32/tests/xor.S
index 72875fe..72875fe 100644
--- a/tests/xor.S
+++ b/riscv/picorv32/tests/xor.S
diff --git a/tests/xori.S b/riscv/picorv32/tests/xori.S
index 7f2207c..7f2207c 100644
--- a/tests/xori.S
+++ b/riscv/picorv32/tests/xori.S