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-rw-r--r--Makefile28
1 files changed, 18 insertions, 10 deletions
diff --git a/Makefile b/Makefile
index 7672b41..0b7c577 100644
--- a/Makefile
+++ b/Makefile
@@ -1,11 +1,15 @@
-TOOLCHAIN_PREFIX = riscv32-unknown-elf-
+TOOLCHAIN_PREFIX = /opt/riscv32i/bin/riscv32-unknown-elf-
-ICE40_SIM_CELLS=$(shell yosys-config --datdir/ice40/cells_sim.v)
+ICE40_SIM_CELLS=$(shell yosys-config --datdir/ecp5/cells_sim.v)
+COPY=cp
# set to 4 for simulation
FIRMWARE_COUNTER_BITS=18
-all: example.bin
+all: example.dfu
+
+dfu: example.dfu
+ dfu-util --alt 0 --download $< --reset
## -------------------
## firmware generation
@@ -23,19 +27,23 @@ firmware.bin: firmware.elf
chmod -x $@
firmware.hex: firmware.bin
- python3 ../../firmware/makehex.py $< 128 > $@
+ python3 picorv32/firmware/makehex.py $< 128 > $@
## ------------------------------
## main flow: synth/p&r/bitstream
-synth.json: example.v ../../picorv32.v firmware.hex
- yosys -v3 -l synth.log -p 'synth_ice40 -top top -json $@; write_verilog -attr2comment synth.v' $(filter %.v, $^)
+synth.json: example.v picorv32/picorv32.v firmware.hex
+ yosys -v3 -l synth.log -p 'synth_ecp5 -top top -json $@; write_verilog -attr2comment synth.v' $(filter %.v, $^)
+
+example_out.config: synth.json example.pcf
+ nextpnr-ecp5 --json $< --textcfg $@ --um5g-85k --speed 8 --package CABGA381 --lpf example.pcf
-example.asc: synth.json example.pcf
- nextpnr-ice40 --hx8k --package ct256 --json $< --pcf example.pcf --asc $@
+example.bit: example_out.config
+ ecppack --compress --freq 38.8 --input $< --bit $@
-example.bin: example.asc
- icepack $< $@
+%.dfu : %.bit
+ $(COPY) $< $@
+ dfu-suffix -v 1209 -p 5af1 -a $@
## -----------------
## icarus simulation