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-rw-r--r--Makefile8
1 files changed, 4 insertions, 4 deletions
diff --git a/Makefile b/Makefile
index 0b7c577..404edf5 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,6 @@
TOOLCHAIN_PREFIX = /opt/riscv32i/bin/riscv32-unknown-elf-
-ICE40_SIM_CELLS=$(shell yosys-config --datdir/ecp5/cells_sim.v)
+ECP5_SIM_CELLS=$(shell yosys-config --datdir/ecp5/cells_sim.v)
COPY=cp
# set to 4 for simulation
@@ -48,7 +48,7 @@ example.bit: example_out.config
## -----------------
## icarus simulation
-example_tb.vvp: example.v example_tb.v ../../picorv32.v firmware.hex
+example_tb.vvp: example.v example_tb.v picorv32/picorv32.v firmware.hex
iverilog -o $@ -s testbench $(filter %.v, $^)
chmod -x $@
@@ -62,7 +62,7 @@ example_sim_vcd: example_tb.vvp
## post-synth simulation
synth_tb.vvp: example_tb.v synth.json
- iverilog -o $@ -s testbench synth.v example_tb.v $(ICE40_SIM_CELLS)
+ iverilog -o $@ -s testbench synth.v example_tb.v $(ECP5_SIM_CELLS)
chmod -x $@
synth_sim: synth_tb.vvp
@@ -78,7 +78,7 @@ route.v: example.asc example.pcf
icebox_vlog -L -n top -sp example.pcf $< > $@
route_tb.vvp: route.v example_tb.v
- iverilog -o $@ -s testbench $^ $(ICE40_SIM_CELLS)
+ iverilog -o $@ -s testbench $^ $(ECP5_SIM_CELLS)
chmod -x $@
route_sim: route_tb.vvp