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-rw-r--r--example.v21
1 files changed, 18 insertions, 3 deletions
diff --git a/example.v b/example.v
index e1c64b4..391115b 100644
--- a/example.v
+++ b/example.v
@@ -1,8 +1,9 @@
`timescale 1 ns / 1 ps
module top (
- input clk,
- output reg LED0, LED1, LED2, LED3, LED4, LED5, LED6, LED7
+ input clk,
+ output reg LED0, LED1, LED2, LED3, LED4, LED5, LED6,
+ output reg [2:0] colour
);
// -------------------------------
// Reset Generator
@@ -71,10 +72,24 @@ module top (
mem_ready <= 1;
end
|mem_wstrb && mem_addr == 32'h1000_0000: begin
- {LED7, LED6, LED5, LED4, LED3, LED2, LED1, LED0} <= mem_wdata;
+ {LED6, LED5, LED4, LED3, LED2, LED1, LED0} <= mem_wdata;
mem_ready <= 1;
end
endcase
end
end
+
+ //always @(posedge clk) begin
+ // LED0 <= 0;
+ // LED1 <= 1;
+ // LED2 <= 0;
+ // LED3 <= 1;
+ // LED4 <= 0;
+ // LED5 <= 1;
+ // LED6 <= 0;
+ //
+ // colour[0] <= 1;
+ // colour[2] <= 1;
+ //end
+
endmodule