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-rw-r--r--picorv32/scripts/yosys/synth_sim.ys8
1 files changed, 0 insertions, 8 deletions
diff --git a/picorv32/scripts/yosys/synth_sim.ys b/picorv32/scripts/yosys/synth_sim.ys
deleted file mode 100644
index ded89d9..0000000
--- a/picorv32/scripts/yosys/synth_sim.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-# yosys synthesis script for post-synthesis simulation (make test_synth)
-
-read_verilog picorv32.v
-chparam -set COMPRESSED_ISA 1 -set ENABLE_MUL 1 -set ENABLE_DIV 1 \
- -set ENABLE_IRQ 1 -set ENABLE_TRACE 1 picorv32_axi
-hierarchy -top picorv32_axi
-synth
-write_verilog synth.v