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Diffstat (limited to 'riscv/Makefile')
| -rw-r--r-- | riscv/Makefile | 112 |
1 files changed, 112 insertions, 0 deletions
diff --git a/riscv/Makefile b/riscv/Makefile new file mode 100644 index 0000000..404edf5 --- /dev/null +++ b/riscv/Makefile @@ -0,0 +1,112 @@ +TOOLCHAIN_PREFIX = /opt/riscv32i/bin/riscv32-unknown-elf- + +ECP5_SIM_CELLS=$(shell yosys-config --datdir/ecp5/cells_sim.v) +COPY=cp + +# set to 4 for simulation +FIRMWARE_COUNTER_BITS=18 + +all: example.dfu + +dfu: example.dfu + dfu-util --alt 0 --download $< --reset + +## ------------------- +## firmware generation + +firmware.elf: firmware.S firmware.c firmware.lds + $(TOOLCHAIN_PREFIX)gcc \ + -DSHIFT_COUNTER_BITS=$(FIRMWARE_COUNTER_BITS) \ + -march=rv32i -Os -ffreestanding -nostdlib \ + -o $@ firmware.S firmware.c \ + --std=gnu99 -Wl,-Bstatic,-T,firmware.lds,-Map,firmware.map,--strip-debug + chmod -x $@ + +firmware.bin: firmware.elf + $(TOOLCHAIN_PREFIX)objcopy -O binary $< $@ + chmod -x $@ + +firmware.hex: firmware.bin + python3 picorv32/firmware/makehex.py $< 128 > $@ + +## ------------------------------ +## main flow: synth/p&r/bitstream + +synth.json: example.v picorv32/picorv32.v firmware.hex + yosys -v3 -l synth.log -p 'synth_ecp5 -top top -json $@; write_verilog -attr2comment synth.v' $(filter %.v, $^) + +example_out.config: synth.json example.pcf + nextpnr-ecp5 --json $< --textcfg $@ --um5g-85k --speed 8 --package CABGA381 --lpf example.pcf + +example.bit: example_out.config + ecppack --compress --freq 38.8 --input $< --bit $@ + +%.dfu : %.bit + $(COPY) $< $@ + dfu-suffix -v 1209 -p 5af1 -a $@ + +## ----------------- +## icarus simulation + +example_tb.vvp: example.v example_tb.v picorv32/picorv32.v firmware.hex + iverilog -o $@ -s testbench $(filter %.v, $^) + chmod -x $@ + +example_sim: example_tb.vvp + vvp -N $< + +example_sim_vcd: example_tb.vvp + vvp -N $< +vcd + +## --------------------- +## post-synth simulation + +synth_tb.vvp: example_tb.v synth.json + iverilog -o $@ -s testbench synth.v example_tb.v $(ECP5_SIM_CELLS) + chmod -x $@ + +synth_sim: synth_tb.vvp + vvp -N $< + +synth_sim_vcd: synth_tb.vvp + vvp -N $< +vcd + +## --------------------- +## post-route simulation + +route.v: example.asc example.pcf + icebox_vlog -L -n top -sp example.pcf $< > $@ + +route_tb.vvp: route.v example_tb.v + iverilog -o $@ -s testbench $^ $(ECP5_SIM_CELLS) + chmod -x $@ + +route_sim: route_tb.vvp + vvp -N $< + +route_sim_vcd: route_tb.vvp + vvp -N $< +vcd + +## --------------------- +## miscellaneous targets + +prog_sram: example.bin + iceprog -S $< + +timing: example.asc example.pcf + icetime -c 62 -tmd hx8k -P ct256 -p example.pcf -t $< + +view: example.vcd + gtkwave $< example.gtkw + +## ------ +## el fin + +clean: + rm -f firmware.elf firmware.map firmware.bin firmware.hex + rm -f synth.log synth.v synth.json route.v example.asc example.bin + rm -f example_tb.vvp synth_tb.vvp route_tb.vvp example.vcd + +.PHONY: all prog_sram view clean +.PHONY: example_sim synth_sim route_sim timing +.PHONY: example_sim_vcd synth_sim_vcd route_sim_vcd |