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author | David Monniaux <david.monniaux@univ-grenoble-alpes.fr> | 2019-05-01 17:04:34 +0200 |
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committer | David Monniaux <david.monniaux@univ-grenoble-alpes.fr> | 2019-05-01 17:04:34 +0200 |
commit | 667c260620b545c04355dd030fc4430790a3a055 (patch) | |
tree | 71729199f610fc8c790502f0e41e1530eaf2ae3f /mppa_k1c/Asmblockgen.v | |
parent | 26a7a6598a80c29a139c533419b38be63c88cd76 (diff) | |
download | compcert-kvx-667c260620b545c04355dd030fc4430790a3a055.tar.gz compcert-kvx-667c260620b545c04355dd030fc4430790a3a055.zip |
translate load.xs
Diffstat (limited to 'mppa_k1c/Asmblockgen.v')
-rw-r--r-- | mppa_k1c/Asmblockgen.v | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/mppa_k1c/Asmblockgen.v b/mppa_k1c/Asmblockgen.v index c2a0a315..7c8a08f6 100644 --- a/mppa_k1c/Asmblockgen.v +++ b/mppa_k1c/Asmblockgen.v @@ -846,6 +846,19 @@ Definition transl_memory_access2 | _, _ => Error (msg "Asmblockgen.transl_memory_access2") end. +Definition transl_memory_access2XS + (chunk: memory_chunk) + (mk_instr: ireg -> ireg -> basic) + (addr: addressing) (args: list mreg) (k: bcode) : res bcode := + match addr, args with + | (Aindexed2XS scale), (a1 :: a2 :: nil) => + assertion (Z.eqb (zscale_of_chunk chunk) scale); + do rs1 <- ireg_of a1; + do rs2 <- ireg_of a2; + OK (mk_instr rs1 rs2 ::i k) + | _, _ => Error (msg "Asmblockgen.transl_memory_access2XS") + end. + Definition transl_memory_access (mk_instr: ireg -> offset -> basic) (addr: addressing) (args: list mreg) (k: bcode) : res bcode := @@ -885,10 +898,15 @@ Definition transl_load_rrr (chunk: memory_chunk) (addr: addressing) do r <- ireg_of dst; transl_memory_access2 (PLoadRRR (chunk2load chunk) r) addr args k. +Definition transl_load_rrrXS (chunk: memory_chunk) (addr: addressing) + (args: list mreg) (dst: mreg) (k: bcode) : res bcode := + do r <- ireg_of dst; + transl_memory_access2XS chunk (PLoadRRR (chunk2load chunk) r) addr args k. + Definition transl_load (chunk: memory_chunk) (addr: addressing) (args: list mreg) (dst: mreg) (k: bcode) : res bcode := match addr with - | Aindexed2XS _ => Error (msg "transl_load Aindexed2XS") + | Aindexed2XS _ => transl_load_rrrXS chunk addr args dst k | Aindexed2 => transl_load_rrr chunk addr args dst k | _ => transl_load_rro chunk addr args dst k end. |