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authorDavid Monniaux <david.monniaux@univ-grenoble-alpes.fr>2019-05-01 19:44:11 +0200
committerDavid Monniaux <david.monniaux@univ-grenoble-alpes.fr>2019-05-01 19:44:11 +0200
commit98be0205d9d29378fb272a9f424144651bd8afec (patch)
treeee9e82956ae521e4a4a47ad8a77e12733cb48f2f /mppa_k1c/Asmblockgenproof1.v
parentaea7e3d6a6b09727724edfa11358111c9a05cd1b (diff)
downloadcompcert-kvx-98be0205d9d29378fb272a9f424144651bd8afec.tar.gz
compcert-kvx-98be0205d9d29378fb272a9f424144651bd8afec.zip
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Diffstat (limited to 'mppa_k1c/Asmblockgenproof1.v')
-rw-r--r--mppa_k1c/Asmblockgenproof1.v83
1 files changed, 78 insertions, 5 deletions
diff --git a/mppa_k1c/Asmblockgenproof1.v b/mppa_k1c/Asmblockgenproof1.v
index ed049539..c9d72c4d 100644
--- a/mppa_k1c/Asmblockgenproof1.v
+++ b/mppa_k1c/Asmblockgenproof1.v
@@ -2110,6 +2110,26 @@ Proof.
inv EV. repeat eexists. eassumption. econstructor; eauto.
Qed.
+Lemma transl_memory_access2XS_correct:
+ forall chunk mk_instr (scale : Z) args k c (rs: regset) m v,
+ transl_memory_access2XS chunk mk_instr scale args k = OK c ->
+ eval_addressing ge rs#SP (Aindexed2XS scale) (map rs (map preg_of args)) = Some v ->
+ exists base ro mro mr1 rs',
+ args = mr1 :: mro :: nil
+ /\ ireg_of mro = OK ro
+ /\ exec_straight_opt (basics_to_code c) rs m (mk_instr base ro ::g (basics_to_code k)) rs' m
+ /\ Val.addl rs'#base (Val.shll rs'#ro (Vint (Int.repr scale))) = v
+ /\ (forall r, r <> PC -> r <> RTMP -> rs'#r = rs#r)
+ /\ scale = (zscale_of_chunk chunk).
+Proof.
+ intros until v; intros TR EV.
+ unfold transl_memory_access2XS in TR; ArgsInv.
+ inv EV. repeat eexists. eassumption. econstructor; eauto.
+ symmetry.
+ apply Z.eqb_eq.
+ assumption.
+Qed.
+
Lemma transl_load_access2_correct:
forall chunk (mk_instr: ireg -> ireg -> basic) addr args k c rd (rs: regset) m v mro mr1 ro v',
args = mr1 :: mro :: nil ->
@@ -2133,6 +2153,32 @@ Proof.
split; intros; Simpl. auto.
Qed.
+Lemma transl_load_access2XS_correct:
+ forall chunk (mk_instr: ireg -> ireg -> basic) (scale : Z) args k c rd (rs: regset) m v mro mr1 ro v',
+ args = mr1 :: mro :: nil ->
+ ireg_of mro = OK ro ->
+ (forall base rs,
+ exec_basic_instr ge (mk_instr base ro) rs m = exec_load_regxs chunk rs m rd base ro) ->
+ transl_memory_access2XS chunk mk_instr scale args k = OK c ->
+ eval_addressing ge rs#SP (Aindexed2XS scale) (map rs (map preg_of args)) = Some v ->
+ Mem.loadv chunk m v = Some v' ->
+ exists rs',
+ exec_straight ge (basics_to_code c) rs m (basics_to_code k) rs' m
+ /\ rs'#rd = v'
+ /\ forall r, r <> PC -> r <> RTMP -> r <> rd -> rs'#r = rs#r.
+Proof.
+ intros until v'; intros ARGS IREGE INSTR TR EV LOAD.
+ exploit transl_memory_access2XS_correct; eauto.
+ intros (base & ro2 & mro2 & mr2 & rs' & ARGSS & IREGEQ & A & B & C & D). rewrite ARGSS in ARGS. inversion ARGS. subst mr2 mro2. clear ARGS.
+ econstructor; split.
+ eapply exec_straight_opt_right. eexact A. apply exec_straight_one. assert (ro = ro2) by congruence. subst ro2.
+ rewrite INSTR. unfold exec_load_regxs. unfold parexec_load_regxs.
+ unfold scale_of_chunk.
+ subst scale.
+ rewrite B, LOAD. reflexivity. Simpl.
+ split; intros; Simpl. auto.
+Qed.
+
Lemma transl_load_access_correct:
forall chunk (mk_instr: ireg -> offset -> basic) addr args k c rd (rs: regset) m v v',
(forall base ofs rs,
@@ -2168,7 +2214,6 @@ Lemma transl_load_memory_access_ok:
Proof.
intros until m. intros ADDR TR ? ?.
unfold transl_load in TR. destruct addr; try contradiction.
- - admit.
- monadInv TR. destruct chunk; ArgsInv; econstructor; (esplit; eauto).
- monadInv TR. destruct chunk. all: ArgsInv; destruct args; try discriminate; monadInv EQ0; eexists; eexists; split; try split;
[ instantiate (1 := (PLoadRRO _ x)); simpl; reflexivity
@@ -2200,6 +2245,27 @@ Proof.
| eauto].
Qed.
+Lemma transl_load_memory_access2XS_ok:
+ forall scale chunk args dst k c rs a v m,
+ transl_load chunk (Aindexed2XS scale) args dst k = OK c ->
+ eval_addressing ge (rs (IR SP)) (Aindexed2XS scale) (map rs (map preg_of args)) = Some a ->
+ Mem.loadv chunk m a = Some v ->
+ exists mk_instr mr0 mro rd ro,
+ args = mr0 :: mro :: nil
+ /\ preg_of dst = IR rd
+ /\ preg_of mro = IR ro
+ /\ transl_memory_access2XS chunk mk_instr (Aindexed2XS scale) args k = OK c
+ /\ forall base rs,
+ exec_basic_instr ge (mk_instr base ro) rs m = exec_load_reg chunk rs m rd base ro.
+Proof.
+ intros until m. intros TR ? ?.
+ unfold transl_load in TR. subst. monadInv TR. destruct chunk. all:
+ unfold transl_memory_access2XS in EQ0; repeat (destruct args; try discriminate); monadInv EQ0; ArgsInv; repeat eexists;
+ [ unfold ireg_of in EQ0; destruct (preg_of m1); eauto; try discriminate; monadInv EQ0; reflexivity
+ | rewrite EQ1; rewrite EQ0; simpl; instantiate (1 := (PLoadRRR _ x)); simpl; rewrite Heqb; reflexivity
+ | eauto].
+Qed.
+
Lemma transl_load_correct:
forall chunk addr args dst k c (rs: regset) m a v,
transl_load chunk addr args dst k = OK c ->
@@ -2211,12 +2277,19 @@ Lemma transl_load_correct:
/\ forall r, r <> PC -> r <> RTMP -> r <> preg_of dst -> rs'#r = rs#r.
Proof.
intros until v; intros TR EV LOAD. destruct addr.
- 1: (* Aindexed2XS *) discriminate.
- 2-4: exploit transl_load_memory_access_ok; eauto; try discriminate;
- intros A; destruct A as (mk_instr & rd & rdEq & B & C); rewrite rdEq;
- eapply transl_load_access_correct; eauto with asmgen.
+ - exploit transl_load_memory_access2XS_ok; eauto. intros (mk_instr & mr0 & mro & rd & ro & argsEq & rdEq & roEq & B & C).
+ rewrite rdEq. eapply transl_load_access2XS_correct; eauto with asmgen. unfold ireg_of. rewrite roEq. reflexivity.
- exploit transl_load_memory_access2_ok; eauto. intros (mk_instr & mr0 & mro & rd & ro & argsEq & rdEq & roEq & B & C).
rewrite rdEq. eapply transl_load_access2_correct; eauto with asmgen. unfold ireg_of. rewrite roEq. reflexivity.
+ - exploit transl_load_memory_access_ok; eauto; try discriminate; try (simpl; reflexivity).
+ intros A; destruct A as (mk_instr & rd & rdEq & B & C); rewrite rdEq;
+ eapply transl_load_access_correct; eauto with asmgen.
+ - exploit transl_load_memory_access_ok; eauto; try discriminate; try (simpl; reflexivity).
+ intros A; destruct A as (mk_instr & rd & rdEq & B & C); rewrite rdEq;
+ eapply transl_load_access_correct; eauto with asmgen.
+ - exploit transl_load_memory_access_ok; eauto; try discriminate; try (simpl; reflexivity).
+ intros A; destruct A as (mk_instr & rd & rdEq & B & C); rewrite rdEq;
+ eapply transl_load_access_correct; eauto with asmgen.
Qed.
Lemma transl_store_access2_correct: