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| -rw-r--r-- | scheduling/InstructionScheduler.ml | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/scheduling/InstructionScheduler.ml b/scheduling/InstructionScheduler.ml index a881df68..4fdc455c 100644 --- a/scheduling/InstructionScheduler.ml +++ b/scheduling/InstructionScheduler.ml @@ -502,6 +502,8 @@ let reg_pres_scheduler (problem : problem) : solution option = * flush stdout; *) if avlregs <= regs_thresholds.(i) then ( + if !Clflags.option_debug_compcert > 6 then + DebugPrint.debug "REGPRES: high pres class %d\n" i; let maybe = InstrSet.sched_CSR i ready usages in (* print_string "maybe\n"; * print_int maybe; |