diff options
| -rw-r--r-- | scheduling/InstructionScheduler.ml | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/scheduling/InstructionScheduler.ml b/scheduling/InstructionScheduler.ml index 4fdc455c..f823ccca 100644 --- a/scheduling/InstructionScheduler.ml +++ b/scheduling/InstructionScheduler.ml @@ -350,7 +350,12 @@ let _ = fun x -> priority_list_scheduler INSTRUCTION_ORDER x;; (* A scheduler sensitive to register pressure *) let reg_pres_scheduler (problem : problem) : solution option = DebugPrint.debug_flag := true; + let nr_instructions = get_nr_instructions problem in + + if !Clflags.option_debug_compcert > 6 then + DebugPrint.debug "SCHEDULING_SUPERBLOCK %d\n" nr_instructions; + let successors = get_successors problem and predecessors = get_predecessors problem and times = Array.make (nr_instructions+1) (-1) in @@ -381,6 +386,7 @@ let reg_pres_scheduler (problem : problem) : solution option = Hashtbl.add live_regs r classe) (Registers.Regset.elements live_regs_entry); + let csr_b = ref false in let counts, mentions = match problem.reference_counting with @@ -502,8 +508,7 @@ let reg_pres_scheduler (problem : problem) : solution option = * flush stdout; *) if avlregs <= regs_thresholds.(i) then ( - if !Clflags.option_debug_compcert > 6 then - DebugPrint.debug "REGPRES: high pres class %d\n" i; + csr_b := true; let maybe = InstrSet.sched_CSR i ready usages in (* print_string "maybe\n"; * print_int maybe; @@ -557,6 +562,9 @@ let reg_pres_scheduler (problem : problem) : solution option = * print_int i; * print_newline (); * flush stdout; *) + if !csr_b && !Clflags.option_debug_compcert > 6 then + DebugPrint.debug "REGPRES: high pres class %d\n" i; + csr_b := false; if !Clflags.option_regpres_temp then cnt := 0; List.iter (fun (r,b) -> |