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-rw-r--r--scheduling/MyRTLpathScheduleraux.ml17
1 files changed, 12 insertions, 5 deletions
diff --git a/scheduling/MyRTLpathScheduleraux.ml b/scheduling/MyRTLpathScheduleraux.ml
index 51c0abc5..30255424 100644
--- a/scheduling/MyRTLpathScheduleraux.ml
+++ b/scheduling/MyRTLpathScheduleraux.ml
@@ -334,11 +334,18 @@ let rename_regs ?only_rename sb code ~liveatentry ~next_free_reg =
in
let code = PTree.set pc inst code in
- let live_renames=
- if is_icond inst then
- update_live_renames pc live_renames fwmap (get_some @@ PTree.get pc sb.liveins)
- else
- live_renames
+ let (live_renames, fwmap)=
+ if is_icond inst then (
+ (* Pretend that registers that are live at an exit already have a definition, so
+ * this catches a couple of edge cases where an instruction was not renamed and
+ * could thus not be moved up. *)
+ let live_regs = Regset.elements @@ get_some @@ PTree.get pc sb.liveins in
+ let fwmap' = Duplicateaux.generate_fwmap live_regs live_regs PTree.empty in
+ let fwmap = my_merge_overwrite fwmap' fwmap in
+ (update_live_renames pc live_renames fwmap (get_some @@ PTree.get pc sb.liveins)
+ , fwmap)
+ ) else
+ (live_renames, fwmap)
in
(code, fwmap, live_renames, next_free_reg)
)