aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
...
* | Select cmpluDavid Monniaux2019-04-052-1/+32
* | select cmpuDavid Monniaux2019-04-058-6/+61
* | factor out some proofsDavid Monniaux2019-04-051-6/+3
* | some more Oselect comparisonsDavid Monniaux2019-04-042-1/+14
* | Merge remote-tracking branch 'origin/mppa-work' into mppa-ternaryDavid Monniaux2019-04-042-352/+187
|\|
| * Refactorisation de forward_simu_basicCyril SIX2019-04-041-102/+55
| * refactorized forward_simu_controlCyril SIX2019-04-041-107/+67
| * Refactorisation de forward_simu_par_controlCyril SIX2019-04-041-141/+63
| * Erreur idiote dans les latences ?Cyril SIX2019-04-041-2/+2
* | ternary ops work on (unsigned/signed) int with test on signed intDavid Monniaux2019-04-041-3/+3
* | more on selectDavid Monniaux2019-04-042-4/+6
* | OselectDavid Monniaux2019-04-042-5/+16
* | progress on OselectDavid Monniaux2019-04-041-19/+35
* | select_soundDavid Monniaux2019-04-044-39/+103
* | some more progress on selectDavid Monniaux2019-04-044-59/+84
* | progressing on selectDavid Monniaux2019-04-042-17/+11
* | working on selectDavid Monniaux2019-04-041-3/+24
* | working on selectDavid Monniaux2019-04-041-28/+58
* | prepare for conditions in cmoveDavid Monniaux2019-04-044-19/+34
* | ternary ops for float/doubleDavid Monniaux2019-04-036-14/+116
* | for floats and doubles, asmgen supportDavid Monniaux2019-04-033-15/+92
* | ternary ops in AES and TEADavid Monniaux2019-04-037-21/+14
* | Merge branch 'mppa-ternary' of gricad-gitlab.univ-grenoble-alpes.fr:sixcy/Com...David Monniaux2019-04-0334-2223/+1151
|\ \
| * | problem in ValueAOpDavid Monniaux2019-04-038-22/+37
| * | begin implementing ternary builtinDavid Monniaux2019-04-032-4/+20
| * | selection of builtin.. progress...David Monniaux2019-04-031-13/+14
| * | some more on builtinsDavid Monniaux2019-04-032-3/+20
| * | attempts at generating builtins, startDavid Monniaux2019-04-033-14/+16
| * | Merge remote-tracking branch 'origin/mppa-work' into mppa-ternaryDavid Monniaux2019-04-0350-3401/+2712
| |\|
| | * Merge remote-tracking branch 'origin/mppa_k1c' into mppa-workCyril SIX2019-04-0314-1456/+421
| | |\
| | | * robustness of Asmblockdeps.*op_eqSylvain Boulmé2019-04-021-27/+38
| | | * comment on Asmblockdeps.is_constantSylvain Boulmé2019-04-021-9/+12
| | | * Impure: improved iandb + struct_eqSylvain Boulmé2019-04-013-34/+28
| | | * renommage abstractbb: Name -> PRegSylvain Boulmé2019-04-015-32/+32
| | | * renommages abstract_bbSylvain Boulmé2019-04-015-156/+156
| | | * petite factorisation de preuveSylvain Boulmé2019-04-011-69/+59
| | | * minor simplSylvain Boulmé2019-04-011-8/+14
| | | * simpler parexec_wio_bblock_auxSylvain Boulmé2019-04-012-3/+2
| | | * cleaning Asmvliw semanticsSylvain Boulmé2019-04-014-42/+73
| | | * delete useless DepExample* filesSylvain Boulmé2019-04-014-1051/+0
| | * | Merge remote-tracking branch 'origin/mppa-work' into mppa-addr-regCyril SIX2019-04-030-0/+0
| | |\ \
| | * | | Load/Store reg-reg are now proven everywhereCyril SIX2019-04-032-92/+68
| | * | | Preuve des load/store registre registre. Reste des modifs mineures dans les p...Cyril SIX2019-04-036-77/+196
| | * | | Preuve du transl_load et transl_store registre offsetCyril SIX2019-04-032-30/+89
| | * | | We now generate load/store with 3 registers (ld rd rs1[rs2]), proofs admittedCyril SIX2019-04-033-494/+51
| | * | | Small refactoring and renaming of Stores and LoadsCyril SIX2019-04-033-70/+50
| | * | | Added definition of PLoadRRR and PStoreRRR - no Asmblockgen generation yetCyril SIX2019-04-0210-205/+417
| | * | | Started to add addressing with register + register, Mach -> Asm not done yetCyril SIX2019-04-015-3/+12
* | | | | Merge remote-tracking branch 'origin/mppa-work' into mppa-ternaryDavid Monniaux2019-04-0232-1238/+1672
|\ \ \ \ \ | | |_|/ / | |/| | |
| * | | | Revert "Started to add addressing with register + register, Mach -> Asm not d...Cyril SIX2019-04-015-12/+3
generated by cgit (git 2.34.1) at 2024-07-11 22:28:20 +0000