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* Exploiting immediate comparisonsCyril SIX2019-05-091-6/+14
* rm Ofslow (résidu du Risc-V, inutilisé et complique les preuves)David Monniaux2019-05-031-2/+2
* does not yet work, arity mismatchDavid Monniaux2019-05-011-0/+1
* it compilesDavid Monniaux2019-05-011-15/+21
* ça avanceDavid Monniaux2019-05-011-7/+7
* translate load.xsDavid Monniaux2019-05-011-1/+19
* indexed2XS beginDavid Monniaux2019-05-011-0/+1
* removed fake ops for int32 -> doubleDavid Monniaux2019-04-291-6/+0
* srsdDavid Monniaux2019-04-291-5/+1
* begin using shrxDavid Monniaux2019-04-291-5/+1
* instruction translation for bitfield insertionDavid Monniaux2019-04-271-0/+12
* some more folding of codeDavid Monniaux2019-04-271-6/+13
* read from bit fieldsDavid Monniaux2019-04-251-0/+14
* make_prologue à partDavid Monniaux2019-04-241-3/+6
* Merge remote-tracking branch 'origin/mppa-work' into mppa-refactorCyril SIX2019-04-081-0/+43
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| * Oselectf, Oselectfs with conditionDavid Monniaux2019-04-051-9/+3
| * selectl with conditionDavid Monniaux2019-04-051-2/+2
| * Select cmpluDavid Monniaux2019-04-051-1/+14
| * select cmpuDavid Monniaux2019-04-051-0/+14
| * some more Oselect comparisonsDavid Monniaux2019-04-041-0/+2
| * OselectDavid Monniaux2019-04-041-1/+11
| * for floats and doubles, asmgen supportDavid Monniaux2019-04-031-8/+4
| * ternary ops in AES and TEADavid Monniaux2019-04-031-1/+1
| * Merge remote-tracking branch 'origin/mppa-work' into mppa-ternaryDavid Monniaux2019-04-031-54/+66
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| * | selectl generationDavid Monniaux2019-03-261-1/+1
| * | selectlDavid Monniaux2019-03-251-0/+7
| * | more on cmoveDavid Monniaux2019-03-251-0/+7
* | | #90 Asmvliw/Asmblock refactoring attemptCyril SIX2019-04-051-3/+3
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* | Preuve du transl_load et transl_store registre offsetCyril SIX2019-04-031-5/+5
* | We now generate load/store with 3 registers (ld rd rs1[rs2]), proofs admittedCyril SIX2019-04-031-9/+40
* | Small refactoring and renaming of Stores and LoadsCyril SIX2019-04-031-48/+28
* | Merge branch 'mppa-mul' into mppa-jumptableDavid Monniaux2019-03-221-12/+0
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| * rm Pdiv / PdivuDavid Monniaux2019-03-221-12/+0
* | begin jumptables (does not work)David Monniaux2019-03-211-2/+3
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* Merge branch 'mppa-madd' into mppa_postpassDavid Monniaux2019-03-201-2/+0
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| * maddl gets to assemblyDavid Monniaux2019-03-201-2/+0
* | Merge branch 'mppa-madd' into mppa_postpassDavid Monniaux2019-03-191-2/+32
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| * mul+madd immediateDavid Monniaux2019-03-191-1/+18
| * mul immediateDavid Monniaux2019-03-191-0/+8
| * maddw dans la générationDavid Monniaux2019-03-181-1/+6
* | Pseudo instruction for 32 bits division, no code generation yetCyril SIX2019-03-191-2/+2
* | Merge branch 'mppa_postpass' of gricad-gitlab.univ-grenoble-alpes.fr:sixcy/Co...Cyril SIX2019-03-181-1/+31
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| * andn / orn long complete I thinkDavid Monniaux2019-03-181-0/+3
| * andn / orn suiteDavid Monniaux2019-03-181-1/+28
* | The parent frame pointer is now R17 instead of R14Cyril SIX2019-03-181-2/+0
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* long nand, nor, nxorDavid Monniaux2019-03-161-0/+21
* nxorDavid Monniaux2019-03-161-0/+7
* nor implementeDavid Monniaux2019-03-161-0/+7
* nand is implementedDavid Monniaux2019-03-161-0/+7
* 32-bit rotate finishedDavid Monniaux2019-03-161-1/+4
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