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| * | | | | | fix broken test MakefileDavid Monniaux2020-03-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | fix math.h so that it does special things only on K1C
* | | | | | | it now works, no more ugly hack to access thread local dataDavid Monniaux2020-02-241-1/+1
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* | | | | | bringing back the ppc64 runtimeDavid Monniaux2020-02-095-0/+440
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* | | | | | why did we remove the ppc runtime ?!David Monniaux2020-02-0817-0/+1430
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* | | | | | Fixed using ccomp assembly preprocessorCyril SIX2020-02-061-3/+3
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* | | | | | Fixing issue with <math.h> and fabsCyril SIX2020-01-091-1/+2
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* | | | | | Merge tag 'v3.6' of https://github.com/AbsInt/CompCert into ↵David Monniaux2019-09-203-0/+156
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| * | | | AArch64 portXavier Leroy2019-08-083-0/+156
| | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a back-end for the AArch64 architecture, namely ARMv8 in 64-bit mode.
* | | | | (#157) Fixing warning for desactivated afaddd builtin. No implementation yetCyril SIX2019-09-051-0/+6
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* | | | | macros for fma() fmaf()David Monniaux2019-08-301-0/+2
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* | | | | fmin/fmax/fminf/fmaxf non bien testésDavid Monniaux2019-08-291-0/+9
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* | | | | merge upstream including fma fixesDavid Monniaux2019-08-2822-1870/+0
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* | | | | Merge branch 'if-conversion' of https://github.com/AbsInt/CompCert into ↵David Monniaux2019-06-031-4/+4
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| * | | | Prepend $(DESTDIR) to the installation target (#169)Bernhard Schommer2019-05-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following the gnu Makefile Conventions the variable $(DESTDIR) should be prepended to all installation commands. This allows staged installs.
* | | | | use all same exact include filesv3.5_k1c_1.2David Monniaux2019-06-031-15/+7
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* | | | added some include filesDavid Monniaux2019-05-292-0/+2
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* | | more builtinsDavid Monniaux2019-05-291-0/+2
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* | | fixes for COSDavid Monniaux2019-05-282-0/+12
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* | directly call float and double division from gcc lib instead of a stubDavid Monniaux2019-05-151-42/+0
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* | 32-bit modulo now uses sign extend then call to the 64-bit functionDavid Monniaux2019-05-131-23/+0
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* | we directly call 64-bit unsigned divisionDavid Monniaux2019-05-131-22/+0
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* | feclearexcept / fetestexceptDavid Monniaux2019-04-131-0/+15
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* | better #include handlingDavid Monniaux2019-04-121-1/+5
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* | workaround for non-standard C isfinite macro in math.hDavid Monniaux2019-04-122-1/+4
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* | simplification of the varargs procedure: they are leaf procedures, there is ↵David Monniaux2019-04-121-40/+1
| | | | | | | | no need to save $ra
* | __builtin_k1_acswapwDavid Monniaux2019-04-112-1/+12
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* | builtin acswapdDavid Monniaux2019-04-112-2/+16
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* | cleaner: put all the special types, defines etc. in one header fileDavid Monniaux2019-04-112-0/+14
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* | passage de structures en varargs (fonctionne avec une convention "passage ↵David Monniaux2019-03-221-0/+3
| | | | | | | | par référence" cohérente avec CompCert mais pas forcément avec gcc)
* | la division flottante fonctionneDavid Monniaux2019-03-202-1/+12
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* | les divisions entieres passentDavid Monniaux2019-03-203-0/+43
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* | sdiv worksDavid Monniaux2019-03-202-1/+15
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* | Added i64_shl and i64_shr to the runtime Makefile, needed by i64_dtosCyril SIX2019-03-191-1/+2
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* | Merge branch 'master' into mppa_postpassCyril SIX2019-03-132-1/+2
|\| | | | | | | | | | | Conflicts: .gitignore runtime/include/stdbool.h
| * <stddef.h>: define NULL with type void *Xavier Leroy2019-02-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ISO C2011 7.19 para 3 says "NULL, which expands to an implementation-defined null pointer constant" ISO C2011 6.3.2.3 para 3 says "An integer constant expression with the value 0, or such an expression cast to type void *, is called a null pointer constant." So, it seems NULL can be defined either as "0" or as "(void *) 0". However, the two definitions are not equivalent in the context of a call to a variadic or unprototyped function: passing 0 when the function expects a pointer value can go wrong if sizeof(int) != sizeof(void *). This commit changes the definition of NULL to the safer one: This is what GCC and Clang do in C mode; they use "#define NULL 0" for C++ only. Fixes issue #265
| * <stdbool.h>: add missing macro __bool_true_false_are_definedXavier Leroy2019-02-041-0/+1
| | | | | | | | | | | | As specified in ISO C99 section 7.16 and C11 section 7.18. Fixes issue #266
* | varargsDavid Monniaux2019-03-101-0/+2
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* | Float conversion fixes + some more conversionsCyril SIX2019-02-271-2/+4
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* | C99 7.16 mandates __bool_true_false_are_definedDavid Monniaux2019-01-301-1/+1
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* | Fixed div64 and mod64Cyril SIX2018-12-112-31/+1
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* | Finished implementation of va_arg + testing doneCyril SIX2018-11-302-1/+73
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* | Merge tag 'v3.4' into mppa_k1cCyril SIX2018-11-211-0/+9
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| * Define the C11 type max_align_t (#115)Bernhard Schommer2018-05-241-0/+9
| | | | | | | | | | | | | | The definition is similar to that of gcc, however since we don't support long doubles out of the box and long doubles are doubles in compat mode we can directly define max_align_t to be long long. Bug 23380
* | Fixed MPPA runtimes not compilingCyril SIX2018-11-202-5/+8
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* | MPPA - Changed division to include the builtinCyril SIX2018-06-051-23/+2
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* | MPPA - div and mod, replaced gcc implementation by C files + ccompCyril SIX2018-05-2113-460/+29
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* | MPPA - Added modulo and division 64 bits. Non certifiedCyril SIX2018-05-2114-0/+595
|/ | | | | | | 32 bits version are not yet there. Right now the code is directly from libgcc, compiled with k1-gcc because of builtins.
* Take advantage of ARMv6T2/ARMv7 instructions even if not in Thumb2 mode (#203)Gergö Barany2017-09-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Clarify that ARMv6 is in fact ARMv6T2 The ARMv6 comes in two flavors depending on the version of the Thumb instruction set supported: ARMv6 for the original Thumb, ARMv6T2 for Thumb2. CompCert only supports Thumb2, so its ARMv6 architecture should really be called ARMv6T2. This makes a difference: the GNU assembler rejects most of the instructions CompCert generates for ARMv6 with "-mthumb" if the architecture is specified as ".arch armv6" as opposed to ".arch armv6t2". This patch fixes the architecture specification in the target printer and the internal name of the architecture. It does not change the configure script's flags to avoid breaking changes. * Always use ARM movw/movt to load large immediates These move-immediate instructions used to be only emitted in Thumb mode, not in ARM mode. As far as I understand ARM's documentation, these instructions are available in *both* modes in ARMv6T2 and above. This should cover all of CompCert's ARM targets. Tested for ARMv6 and ARMv7, both with and without Thumb2. The behavior is now identical to Clang, and the GNU assembler accepts these instructions in all configurations. * Separate ARMv6 and ARMv6T2; no movw/movt on ARMv6 - define separate architecture models for ARMv6 and ARMv6T2 - introduce `Archi.move_imm` parameter on ARM to identify models with `movw`/`movt` move-immediate instructions (all except ARMv6, in both ARM and Thumb mode) * Fixes for support for architectures with Thumb2 - rename relevant parameter to `Archi.thumb2_support` - on ARMv6 without Thumb2, silently accept -marm flag (but not -mthumb) - allow generation of `sbfx` in ARM mode if Thumb2 is supported
* Prefixed runtime functions.Bernhard Schommer2017-08-2557-208/+208
| | | | | | | The runtime functions are prefixed with compcert in order to avoid potential clashes with runtime/builtin functions of other compilers. Bug 22062
* Hybrid 64bit/32bit PowerPC portBernhard Schommer2017-05-0315-435/+200
| | | | | | | | | | | | | This commit adds code generation for 64bit PowerPC architectures which execute 32bit applications. The main difference to the normal 32bit PowerPC port is that it uses the available 64bit instructions instead of using the runtime library functions. However pointers are still 32bit and the 32bit calling convention is used. In order to use this port the target architecture must be either in Server execution mode or if in Embedded execution mode the high order 32 bits of GPRs must be implemented in 32-bit mode. Furthermore the operating system must preserve the high order 32 bits of GPRs.
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