diff options
| author | Xavier Leroy <xavierleroy@users.noreply.github.com> | 2015-04-22 14:27:12 +0200 |
|---|---|---|
| committer | Xavier Leroy <xavierleroy@users.noreply.github.com> | 2015-04-22 14:27:12 +0200 |
| commit | 0bf99217426a44046ef0aaa7f84a9b2a3646ed89 (patch) | |
| tree | e4f983980a5001792b90ed8f3dbd8fa241e43eb1 /ia32/Machregsaux.ml | |
| parent | 08b2b46f15e70b11c044e4e9a7c8438a96d57ed7 (diff) | |
| parent | ca4aa822693f4d98de99fd3f13c1523d733e1cb0 (diff) | |
| download | compcert-0bf99217426a44046ef0aaa7f84a9b2a3646ed89.tar.gz compcert-0bf99217426a44046ef0aaa7f84a9b2a3646ed89.zip | |
Merge pull request #40 from AbsInt/inline-asm
GCC-style extended inline asm.
The subset implemented is:
- zero or one output
- output constraints "=r" (to register) or "=m" (to memory)
- zero, one or several inputs
- input constraints "r" (in register), "m" (in memory), "i" and "n" (compile-time integer constant)
- clobbered registers (the 3rd argument)
- both anonymous (%3) and named (%[name]) operands
- modifiers %R and %Q to refer to the most significant / least significant part of a register pair holding a 64-bit integer. (Undocumented GCC ARM feature.)
All asm statements are treated as "volatile", possibly modifying memory and condition codes.
Diffstat (limited to 'ia32/Machregsaux.ml')
| -rw-r--r-- | ia32/Machregsaux.ml | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/ia32/Machregsaux.ml b/ia32/Machregsaux.ml index 8403746a..3083cf3e 100644 --- a/ia32/Machregsaux.ml +++ b/ia32/Machregsaux.ml @@ -15,8 +15,8 @@ open Machregs let register_names = [ - ("AX", AX); ("BX", BX); ("CX", CX); ("DX", DX); - ("SI", SI); ("DI", DI); ("BP", BP); + ("EAX", AX); ("EBX", BX); ("ECX", CX); ("EDX", DX); + ("ESI", SI); ("EDI", DI); ("EBP", BP); ("XMM0", X0); ("XMM1", X1); ("XMM2", X2); ("XMM3", X3); ("XMM4", X4); ("XMM5", X5); ("XMM6", X6); ("XMM7", X7); ("ST0", FP0) |