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author | Xavier Leroy <xavierleroy@users.noreply.github.com> | 2016-08-24 11:24:59 +0200 |
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committer | GitHub <noreply@github.com> | 2016-08-24 11:24:59 +0200 |
commit | 0a7288fb65ebaed329e06c1fd14aef83e8defcda (patch) | |
tree | c2c7ac666c62be0f97a20c74286e0457890ddd8d /runtime/arm/i64_udivmod.S | |
parent | 954b01e1ac6189f4a8b5ad1b6accf6eb01261d1f (diff) | |
parent | e0f0f573a4a8fc1f564a31388afa9c23e48bb016 (diff) | |
download | compcert-0a7288fb65ebaed329e06c1fd14aef83e8defcda.tar.gz compcert-0a7288fb65ebaed329e06c1fd14aef83e8defcda.zip |
Merge pull request #118 from AbsInt/armeb
Support for ARM Big Endian
Diffstat (limited to 'runtime/arm/i64_udivmod.S')
-rw-r--r-- | runtime/arm/i64_udivmod.S | 66 |
1 files changed, 33 insertions, 33 deletions
diff --git a/runtime/arm/i64_udivmod.S b/runtime/arm/i64_udivmod.S index e5373ad4..4ba99bc9 100644 --- a/runtime/arm/i64_udivmod.S +++ b/runtime/arm/i64_udivmod.S @@ -17,7 +17,7 @@ @ * Neither the name of the <organization> nor the @ names of its contributors may be used to endorse or promote products @ derived from this software without specific prior written permission. -@ +@ @ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS @ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT @ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -38,42 +38,42 @@ @@@ Auxiliary function for division and modulus. Don't call from C -@ On entry: N = (r0, r1) numerator D = (r2, r3) divisor -@ On exit: Q = (r4, r5) quotient R = (r0, r1) remainder -@ Locals: M = (r6, r7) mask TMP = r8 temporary - +@ On entry: N = (r0, r1) numerator D = (r2, r3) divisor +@ On exit: Q = (r4, r5) quotient R = (r0, r1) remainder +@ Locals: M = (r6, r7) mask TMP = r8 temporary + FUNCTION(__i64_udivmod) - orrs r8, r2, r3 @ is D == 0? - it eq - bxeq lr @ if so, return with unspecified results - MOV r4, #0 @ Q = 0 - MOV r5, #0 - MOV r6, #1 @ M = 1 - MOV r7, #0 -1: cmp r3, #0 @ while ((signed) D >= 0) ... + orrs r8, Reg1LO, Reg1HI @ is D == 0? + it eq + bxeq lr @ if so, return with unspecified results + MOV Reg2LO, #0 @ Q = 0 + MOV Reg2HI, #0 + MOV Reg3LO, #1 @ M = 1 + MOV Reg3HI, #0 +1: cmp Reg1HI, #0 @ while ((signed) D >= 0) ... blt 2f - subs r8, r0, r2 @ ... and N >= D ... - sbcs r8, r1, r3 + subs r8, Reg0LO, Reg1LO @ ... and N >= D ... + sbcs r8, Reg0HI, Reg1HI blo 2f - adds r2, r2, r2 @ D = D << 1 - adc r3, r3, r3 - adds r6, r6, r6 @ M = M << 1 - adc r7, r7, r7 + adds Reg1LO, Reg1LO, Reg1LO @ D = D << 1 + adc Reg1HI, Reg1HI, Reg1HI + adds Reg3LO, Reg3LO, Reg3LO @ M = M << 1 + adc Reg3HI, Reg3HI, Reg3HI b 1b -2: subs r0, r0, r2 @ N = N - D - sbcs r1, r1, r3 - orr r4, r4, r6 @ Q = Q | M - orr r5, r5, r7 - bhs 3f @ if N was >= D, continue - adds r0, r0, r2 @ otherwise, undo what we just did - adc r1, r1, r3 @ N = N + D - bic r4, r4, r6 @ Q = Q & ~M - bic r5, r5, r7 -3: lsrs r7, r7, #1 @ M = M >> 1 - rrx r6, r6 - lsrs r3, r3, #1 @ D = D >> 1 - rrx r2, r2 - orrs r8, r6, r7 @ repeat while (M != 0) ... +2: subs Reg0LO, Reg0LO, Reg1LO @ N = N - D + sbcs Reg0HI, Reg0HI, Reg1HI + orr Reg2LO, Reg2LO, Reg3LO @ Q = Q | M + orr Reg2HI, Reg2HI, Reg3HI + bhs 3f @ if N was >= D, continue + adds Reg0LO, Reg0LO, Reg1LO @ otherwise, undo what we just did + adc Reg0HI, Reg0HI, Reg1HI @ N = N + D + bic Reg2LO, Reg2LO, Reg3LO @ Q = Q & ~M + bic Reg2HI, Reg2HI, Reg3HI +3: lsrs Reg3HI, Reg3HI, #1 @ M = M >> 1 + rrx Reg3LO, Reg3LO + lsrs Reg1HI, Reg1HI, #1 @ D = D >> 1 + rrx Reg1LO, Reg1LO + orrs r8, Reg3LO, Reg3HI @ repeat while (M != 0) ... bne 2b bx lr ENDFUNCTION(__i64_udivmod) |