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* | | Use R10 in atomic compare and exchange for the rlwinm.Bernhard Schommer2015-09-221-2/+2
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* | | Fix typo dest -> dstMichael Schmidt2015-09-221-9/+9
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* | | Merge pull request #54 from AbsInt/atomic-builtinsBernhard Schommer2015-09-211-5/+56
|\ \ \ | |/ / |/| | Atomic builtins
| * | Removed unnecessary move register and use the correct register as base value ↵Bernhard Schommer2015-09-211-3/+2
| | | | | | | | | | | | for the rlwinm.
| * | Applied a few simplification for temporary registers.Bernhard Schommer2015-09-211-13/+14
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| * | Integrated the fix of commit de40fce9c16ced8d23389cbcfc55ef6d99466fe8 for ↵Bernhard Schommer2015-09-171-11/+3
| | | | | | | | | | | | the atomics.
| * | Removed usage of bne and removed duplicated code for return values of atomics.Bernhard Schommer2015-09-151-39/+19
| | | | | | | | | | | | | | | | | | | | | Instead of introducing a new bne instruction in Asm.v and the TargetPrinter.ml I use the equivalent bf instruction. The duplicated code is due to unused return values of builtins. Now we only emit the additional code for the return value if the return value is used instead of duplicating the whole emiting sequence.
| * | Use fix registers for atomic builtins.Bernhard Schommer2015-09-141-9/+33
| | | | | | | | | | | | | | | | | | In order to avoid clashes during register allocation etc. The builtins now use fixed registers and mark additional registers as destroyed for temporaries.
| * | Use the gcc version of atomic load.Bernhard Schommer2015-09-111-3/+1
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| * | Added builtin for atomic compare and exchange.Bernhard Schommer2015-09-101-1/+1
| | | | | | | | | | | | | | | | | | The new __builtin_atomic_compare_exchange(int *ptr,int *exp,int *dsr); writes dsr into ptr if ptr is equal to exp and returns true if ptr is not equal to exp it writes ptr into exp and returns false.
| * | Merge branch 'master' into atomic-builtinsBernhard Schommer2015-09-101-0/+37
| |\| | | | | | | | | | | | | Conflicts: powerpc/CBuiltins.ml
| * | Add builtin for atomic load.Bernhard Schommer2015-09-091-0/+9
| | | | | | | | | | | | | | | | | | Implement the new __builtin_atomic_load(int *a, int *b); which stores *a in *b. This differs from the atomic_load of the GCC, since the PPC ISA manual states that you must jump before the load again if it fails.
| * | Added an builtin for the atomic exchange operation.Bernhard Schommer2015-09-091-5/+16
| |/ | | | | | | | | The new builtin __builtin_atomic_exchange(int *a, int *b, int *c) stores *b in *a and sets *c to the old value of *a.
* / correct error message for __builtin_dcbtlsMichael Schmidt2015-09-181-1/+1
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* Added builtin for isel.Bernhard Schommer2015-09-081-0/+4
| | | | | The builtin_isel function takes a _Bool as first argument and returns either the second or the third depending on the value of the _Bool.
* Added builtins for call frame and return address.Bernhard Schommer2015-09-071-2/+17
| | | | | | This builtins can be used to get the call frame address and the return address. To correctly compute the load address of the return address the allocframe is extended to contain the offset of the return address.
* Added builtin for the cmpb instruction.Bernhard Schommer2015-09-071-0/+2
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* Simplified generation of builtins for cache instructions.Bernhard Schommer2015-09-071-57/+18
| | | | | | The cache instructions need no special constraint on the address argument. Therefore also the generation of the address is no longer needed.
* Added builtin for mbar instruction.Bernhard Schommer2015-09-031-0/+6
| | | | This commit adds a builtin function for the mbar instruction.
* New builtin for dcbz instruction.Bernhard Schommer2015-09-031-4/+6
| | | | | | This commit adds a builtin for the dcbz instructions. Additionally the dcbt,dcbtst,dcbtls and icbtls instruction are changed to their actually form all taking one additional register in Asm.v.
* Added builtin for the icbtls instruction.Bernhard Schommer2015-09-021-0/+10
| | | | This commit adds a builtin for the icbtls instruction.
* Allow only CT values of 0 and 2 in dcbtls instruction.Bernhard Schommer2015-09-021-1/+1
| | | | | The dcbtls instruction allows only the values 0 and 2 according to the PPC Isa.
* Added builtin for dcbtlsBernhard Schommer2015-09-021-9/+50
| | | | | | THis commit adds a builtin function for the dcbtls instruction. Additionaly it changes the printing of the dcbt and dcbtst instruction to embedded mode and adds support for different address variants.
* Added the gcc builtin prefetch.Bernhard Schommer2015-09-011-0/+11
| | | | | | This commit implements the gcc __builtin_prefetch in a form with all arguments for the powerpc architecture. The resulting instructions are the dcbt and dcbtst instructions in Server Category.
* Improve error reporting in Asmexpand.Xavier Leroy2015-08-241-19/+32
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* Renaming {BA,BR}_longofwords -> {BA,BR}_splitlong.Xavier Leroy2015-08-221-19/+17
| | | | | | | | Use EF_debug instead of EF_annot for line number annotations. Introduce PrintAsmaux.print_debug_info (very incomplete). powerpc/Asmexpand: revise expand_memcpy_small.
* Adapt the PowerPC port to the new builtin representation.Xavier Leroy2015-08-211-168/+189
| | | | | | | __builtin_get_spr() and __builtin_set_spr() work, but horrible error message if the SPR argument is not a constant. powerpc/AsmToJSON.ml needs updating.
* Added builtin for the dcbf instructionBernhard Schommer2015-08-171-0/+2
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* Merge pull request #46 from AbsInt/asmexpandXavier Leroy2015-08-171-44/+11
|\ | | | | Merge branch 'asmexpand' of github.com:AbsInt/CompCert
| * Merge branch 'master' into asmexpandBernhard Schommer2015-07-141-4/+5
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| * | Merge branch 'asmexpand' of github.com:AbsInt/CompCertBernhard Schommer2015-06-261-44/+11
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| * | Revert "Merge branch 'asmexpand' of github.com:AbsInt/CompCert"Bernhard Schommer2015-06-261-11/+44
| | | | | | | | | | | | | | | This reverts commit 777566e81b9762d6bdc773a1f63d56a7ac97433c, reversing changes made to daf9ac64fc9611ecf09d70560a6fa1ba80b9c9c1.
| * | Merge branch 'asmexpand' of github.com:AbsInt/CompCertBernhard Schommer2015-06-261-44/+11
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| | * | Moved the printing of the builtin functions etc. into Asmexpand for ARM in ↵Bernhard Schommer2015-06-101-44/+11
| | | | | | | | | | | | | | | | the same way as it is done for PPC.
* | | | Added builtin for the dcbi instruction.Bernhard Schommer2015-08-171-0/+2
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* | | | Added builitin for the icbi instruction.Bernhard Schommer2015-08-141-0/+2
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* | | | Added builtin for the lwsync barrier.Bernhard Schommer2015-08-141-0/+2
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* | | Set/clear CR6 before calling an unprototyped function.Xavier Leroy2015-07-071-3/+4
| | | | | | | | | | | | | | | | | | A function declared without a prototype could be implemented by a vararg function (even though this is undefined behavior in C99). Be nice in this case.
* | | Corrected little typo in __builtin_clz function.Bernhard Schommer2015-07-061-1/+1
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* / Changed a minor typo: Pstwxu should be PstwuxBernhard Schommer2015-06-221-1/+1
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* Support for GCC-style extended asm, continued:Xavier Leroy2015-04-211-1/+1
| | | | | | | | - support "r", "m" and "i" constraints - support "%Q" and "%R" modifiers for register pairs - support register clobbers - split off analysis and transformation of asm statements in cparser/ExtendedAsm.ml
* Experiment: support a subset of GCC's extended asm statements.Xavier Leroy2015-04-171-1/+1
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* Updating the PowerPC and ARM ports.Xavier Leroy2015-03-271-1/+1
| | | | PowerPC: always use full register names to print annotations.
* Cold feet: suppress builtins for load with reservation/store conditional, ↵xleroy2014-08-281-6/+0
| | | | | | use case is unclear. git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2622 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
* Rename __builtin_cntlz to __builtin_clz.xleroy2014-08-271-1/+1
| | | | | | | IA32: add __builtin_clz, __builtin_ctz. git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2619 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
* Add builtins for load with reservation and conditional store.xleroy2014-08-201-0/+6
| | | | git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2613 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
* powerpc/Asm: simplify the modeling of Csymbol_low and Csymbol_high.xleroy2014-08-181-6/+26
| | | | | | | | | | | powerpc/Asmgen*: simplify the code generated for far-data relative accesses, so that the only occurrences of Csymbol_rel_{low,high} are in the pattern Paddis(r, GPR0, Csymbol_rel_high...); Paddi(r, r, Csymbol_rel_low...) checklink/Check.ml: check the pattern above. git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2569 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
* All targets: add __builtin_membarxleroy2014-07-281-7/+9
| | | | | | | ARM: add __builtin_dsb __builtin_isb git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2554 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
* PowerPC port: refactored the expansion of built-in functions andxleroy2014-07-281-0/+525
pseudo-instructions so that it does not need to be re-done in cchecklink. cchecklink: updated accordingly. testsuite: compile with -sdump and run cchecklink if supported. git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2553 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
generated by cgit (git 2.34.1) at 2024-07-01 16:40:16 +0000