| Commit message (Collapse) | Author | Age | Files | Lines |
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Implement the new __builtin_atomic_load(int *a, int *b); which stores
*a in *b. This differs from the atomic_load of the GCC, since the PPC
ISA manual states that you must jump before the load again if it fails.
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The new builtin __builtin_atomic_exchange(int *a, int *b, int *c)
stores *b in *a and sets *c to the old value of *a.
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The builtin_isel function takes a _Bool as first argument and returns
either the second or the third depending on the value of the _Bool.
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This builtins can be used to get the call frame address and the return
address. To correctly compute the load address of the return address
the allocframe is extended to contain the offset of the return address.
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The cache instructions need no special constraint on the address
argument. Therefore also the generation of the address is no longer
needed.
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This commit adds a builtin function for the mbar instruction.
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This commit adds a builtin for the dcbz instructions. Additionally
the dcbt,dcbtst,dcbtls and icbtls instruction are changed to their
actually form all taking one additional register in Asm.v.
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This commit adds a builtin for the icbtls instruction.
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The dcbtls instruction allows only the values 0 and 2 according to
the PPC Isa.
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THis commit adds a builtin function for the dcbtls instruction.
Additionaly it changes the printing of the dcbt and dcbtst instruction to
embedded mode and adds support for different address variants.
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This commit implements the gcc __builtin_prefetch in a form with all
arguments for the powerpc architecture. The resulting instructions are
the dcbt and dcbtst instructions in Server Category.
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Use EF_debug instead of EF_annot for line number annotations.
Introduce PrintAsmaux.print_debug_info (very incomplete).
powerpc/Asmexpand: revise expand_memcpy_small.
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__builtin_get_spr() and __builtin_set_spr() work, but horrible error
message if the SPR argument is not a constant.
powerpc/AsmToJSON.ml needs updating.
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Merge branch 'asmexpand' of github.com:AbsInt/CompCert
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This reverts commit 777566e81b9762d6bdc773a1f63d56a7ac97433c, reversing
changes made to daf9ac64fc9611ecf09d70560a6fa1ba80b9c9c1.
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the same way as it is done for PPC.
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A function declared without a prototype could be implemented by a
vararg function (even though this is undefined behavior in C99).
Be nice in this case.
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- support "r", "m" and "i" constraints
- support "%Q" and "%R" modifiers for register pairs
- support register clobbers
- split off analysis and transformation of asm statements in
cparser/ExtendedAsm.ml
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PowerPC: always use full register names to print annotations.
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use case is unclear.
git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2622 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
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IA32: add __builtin_clz, __builtin_ctz.
git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2619 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
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git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2613 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
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powerpc/Asmgen*: simplify the code generated for far-data relative
accesses, so that the only occurrences of Csymbol_rel_{low,high}
are in the pattern
Paddis(r, GPR0, Csymbol_rel_high...); Paddi(r, r, Csymbol_rel_low...)
checklink/Check.ml: check the pattern above.
git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2569 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
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ARM: add __builtin_dsb __builtin_isb
git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2554 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
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pseudo-instructions so that it does not need to be re-done in
cchecklink.
cchecklink: updated accordingly.
testsuite: compile with -sdump and run cchecklink if supported.
git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@2553 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e
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