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* Move Z definitions out of Integers and into ZbitsXavier Leroy2019-04-262-9/+10
| | | | | | | | | | The module Integers.Make contained lots of definitions and theorems about Z integers that were independent of the word size. These definitions and theorems are useful outside Integers.Make, but it felt unnatural to fetch them from modules Int or Int64. This commit moves the word-size-independent definitions and theorems to a new module, lib/Zbits.v, and fixes their uses in the code base.
* Upgrade embedded version of Flocq to 3.1.Guillaume Melquiond2019-03-271-11/+14
| | | | | | | | | | | | Main changes to CompCert outside of Flocq are as follows: - Minimal supported version of Coq is now 8.7, due to Flocq requirements. - Most modifications are due to Z2R being dropped in favor of IZR and to the way Flocq now handles NaNs. - CompCert now correctly handles NaNs for the Risc-V architecture (hopefully).
* Fix typo in asmexpand. Bug 24953Bernhard Schommer2018-11-071-1/+1
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* Use 'gpr_or_zero' for base register of indexed load/stores, bug 24776Michael Schmidt2018-10-202-5/+10
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* Switch conditions for eref plattforms.Bernhard Schommer2018-09-191-4/+4
| | | | | Otherwise an isel is generated if no isel is needed at all. Bug 24516
* Support __builtin_isel64 for non-EREF PPC64 platforms (#141)Xavier Leroy2018-09-181-22/+28
| | | | | | If the isel instruction is missing, it can be emulated just like we do in the 32-bit case (__builtin_isel). Follow-up to commit 51d32b92. Bug 24516
* Add builtin isel (conditional move) for int64, uint64 and _Bool (#140)Bernhard Schommer2018-09-182-1/+16
| | | | | New builtin isel variants to support conditional moves for 64bit integers and _Bool values. Bug 24516
* Improved diagnostics: spelling, wording, etc (#138)Michael Schmidt2018-09-141-1/+1
| | | | | | | | | | | | | | | | | | * bug 24268: avoid assertion after reporting error for invalid call to builtin_debug * bug 24268, remove duplicated warning tag in lexer messages * bug 24268, fix spelling in array element designator message * bug 24268, unify 'consider adding option ...' messages * bug 24268, add spacing for icbi operands * bug 24268, uniform use of Ignored_attributes class for identical warnings * bug 24268, unify message for 'assignment to const type' to error from error/fatal error * bug 24268, in handcrafted.messages, "a xxx have been recognized" -> "a xxx has been recognized"
* Generate a nop instruction after some ais annotations (#137)Bernhard Schommer2018-09-122-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | * Generate a nop instruction after ais annotations. In order to prevent the merging of ais annotations with following Labels a nop instruction is inserted, but only if the annotation is followed immediately by a label. The insertion of nop instructions is performed during the expansion of builtin and pseudo assembler instructions and is processor independent, by inserting a __builtin_nop built-in. * Add Pnop instruction to ARM, RISC-V, and x86 ARM as well as RISC-V don't have nop instructions that can be easily encoded by for example add with zero instructions. For x86 we used to use `mov X0, X0` for nop but this may not be as efficient as the true nop instruction. * Implement __builtin_nop on all supported target architectures. This builtin is not yet made available on the C side for all architectures. Bug 24067
* Fix typo in pattern match of error case, bug 24326Michael Schmidt2018-08-221-1/+1
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* Added Pldi to instr_size.Bernhard Schommer2018-08-011-0/+1
| | | | | | Since Pldi generates two instructions instr_size of Pldi should return 2. Bug 24218
* Model external calls as destroying all caller-save registersXavier Leroy2018-06-012-3/+12
| | | | | | | | | | The semantics of external function calls in LTL, Linear, Mach and Asm now consider that all caller-save registers are set to Vundef by the call. This models that fact that the external function can modify those registers arbitrarily. Update the proofs of the Allocation, Tunneling, Stacking and Asmgen passes accordingly.
* Add missing tab character, bug 23541Michael Schmidt2018-05-021-1/+1
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* Add new powerpc builtins.Michael Schmidt2018-04-275-4/+44
| | | | | | New builtin for 64-bit load/store with byte reversal and 64-bit mul-high. Bug 23541
* Print symbols as symbols.Bernhard Schommer2018-03-081-16/+19
| | | | | | This allows us to replacing them by their address in valex and additionally checking them. Bug 22438
* Use binary output.Bernhard Schommer2018-03-071-1/+1
| | | | | | This should avoid problems when newlines are used in string constants etc. Bug 23172
* Reactivated and improved ais annotations.Bernhard Schommer2018-03-061-9/+10
| | | | | | | | | | | | | | | | | | The ais annotations are now handled in a separate file shared between all architectures. Also two different variants of replacements are supported, %e which expands to ais expressions and %l which also expands to an ais expression but is guaranted to be usable as l-value in the ais annotation. Otherwise the new warning is Wrong_is_parameter is generated. Also an error message is generated if floating point variables are used in ais annotations since a3 does not support them at the moment. Additionally an error message is generated for plain volatile variables used, since they will enforce a volatile load and result in the value being passed to the annotation instead of the address as other global variables.
* Improve strength reduction of unsigned comparisons x ==u 0, x !=u 0, etc (#59)Xavier Leroy2018-02-162-6/+55
| | | | | | | | | | | | | | | | | | | When x is known to be either 0 or 1, comparisons such as x == 0 x != 0 x == 1 x != 1 can be optimized away. This optimization was already performed for signed comparisons. This commit extends the optimization to unsigned comparisons as well. Additionally, for PowerPC only, some unsigned (dis)equality comparisons are turned into signed comparisons when we know it makes no difference, i.e. when both arguments are guaranteed not to be pointers. The reason is that Asmgen can produce shorter instruction sequences for some signed equality comparisons than for the corresponding unsigned comparisons. It's important to optimize unsigned integer comparisons because casts to the C99 type _Bool are compiled as x !=u 0 unsigned comparisons. In particular, cascades of casts to _Bool are now reduced to a single cast much more often than before.
* Refactor the handling of errors and warnings (#44)Bernhard Schommer2018-02-081-1/+1
| | | | | | | | | | | | | | | | | * Module Cerrors is now called Diagnostic and can be used in parts of CompCert other than cparser/ * Replaced eprintf error. Instead of having eprintf msg; exit 2 use the functions from the Diagnostics module. * Raise on error before calling external tools. * Added diagnostics to clightgen. * Fix error handling of AsmToJson. * Cleanup error handling of Elab and C2C. *The implementation of location printing (file & line) is simplified and correctly prints valid filenames with invalid lines.
* Change AsmToJson to be similar to other printers.Bernhard Schommer2018-01-052-5/+17
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* Resynchronize the LICENSE file and the license headers in individual files (#45)Xavier Leroy2018-01-051-0/+3
| | | | | | | | | | | Some files are dual-licensed (GPL + noncommercial license), as marked redundantly in the license headers of those files, and in the LICENSE file. OVer the years those two markings got inconsistent. This commit updates the LICENSE file and the license headers of some files so that they agree on which files are dual-licensed. Some build-related files were dual-licensed but some others were not. Fixed by dual-licensing configure, Makefile.menhir, extraction/extraction.v, */extractionMachdep.v Moved lib/Json* to backend/ because there is no need to dual-license those files, yet lib/* is dual-licensed. Plus: JsonAST did not really belong in lib/ anyway, as it depends on AST which is not in lib/
* Optimization for division by one during constant propagation (#39)Michael Schmidt2017-12-052-6/+13
| | | | Signed and unsigned divisions by literal 1 are already optimized away during the Selection phase. This pull request also optimizes those divisions when the 1 divisor is produced by constant propagation.
* New json printing interface.Bernhard Schommer2017-11-141-143/+18
| | | | | The common json export functionallity is moved into an own File. Bug 22472
* Remove no longer used function. Bug 22525Bernhard Schommer2017-11-101-2/+0
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* Removed no longer used function. Bug 22525Bernhard Schommer2017-11-091-30/+0
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* Fix jumptable issue.Bernhard Schommer2017-11-081-1/+1
| | | | | | Instead of using reset_constants use reset_literals which avoids emptying the jumptables. Bug 22525
* Simplifiy handling of constant emmitting.Bernhard Schommer2017-11-081-20/+14
| | | | | | Instead of just storing the constants in a list, they are now stored in a hashtable. This avoids printing of duplicates. Bug 22525
* Remove superfluous function.Bernhard Schommer2017-11-061-2/+0
| | | | | The new_label function is alway equal to PrintAsmaux.new_label. Bug 22472
* Merge pull request #191 from sigurdschneider/masterXavier Leroy2017-10-201-0/+1
|\ | | | | | | Ensure FunInd or Recdef is imported if functional induction is used. This is necessary for Coq 8.7.0.
| * Ensure FunInd or Recdef is imported if functional induction is usedSigurd Schneider2017-07-201-0/+1
| | | | | | | | | | | | Coq 8.7 does not load FunInd in prelude anymore, so this is necessary. Recdef exports FunInd, so if Recdef is imported, importing FunInd is not required.
* | New support for inserting ais-annotations.Bernhard Schommer2017-10-194-13/+29
| | | | | | | | | | | | | | | | | | | | | | | | The ais annotations can be inserted via the new ais variants of the builtin annotation. They mainly differe in that they have an address format specifier '%addr' which will be replaced by the adress in the binary. The implementation simply prints a label for the builtin call alongside a the text of the annotation as comment and inserts the annotation together as acii string in a separate section 'ais_annotations' and replaces the usages of the address format specifiers by the address of the label of the builtin call.
* | Make the list unique. Bug 22239Bernhard Schommer2017-09-261-177/+22
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* | Moved common buitlins to C2C gernic_builtins.Bernhard Schommer2017-09-261-8/+0
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* | Added dump-mnemonics option.Bernhard Schommer2017-09-252-0/+186
| | | | | | | | | | | | This option allows it to dump a list of all used mnemonics into a file. Bug 22239
* | Remove coq warnings (#28)Bernhard Schommer2017-09-225-23/+23
| | | | | | | | Replace deprecated functions and theorems from the Coq standard library (version 8.6) by their non-deprecated counterparts.
* | Disallow usage of default pattern for AsmToJSON.Bernhard Schommer2017-09-221-2/+11
| | | | | | | | | | | | | | In order to ensure that no new instruction is added without adding it to the Json export we enforce warning 4 for the instruction printer and removed all default pattern matchings. Bug 22239
* | Fixed typo.Bernhard Schommer2017-08-241-1/+1
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* | Added annot to json dump.Bernhard Schommer2017-07-241-3/+20
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* | Print_annot should produce a string.Bernhard Schommer2017-07-191-5/+5
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* Constprop strength reduction (#17)Bernhard Schommer2017-07-123-16/+304
| | | | | | | PowerPC port: add strength reduction for 64-bit operations * Added strength reduction for 64bit compare, subl, addl, mull, andl, orl, xorl, divl, shll, shrl, shrlu, shrluimm, shllimm, mullimm, divlu. (Bug 21748) * Moved shru_rolml proof to Values.
* Extend builtin arguments with a pointer addition operator, continuedXavier Leroy2017-07-065-87/+179
| | | | | | | | - Add support for PowerPC, with all addressing modes. - Add support for ARM, with "reg + ofs" addressing mode. - Add support for RISC-V, with the one addressing mode. - Constprop.v: forgot to recurse in BA_addptr - volatile4 test: more tests
* Issue #16P: wrong rlwinm instruction generated by constant propagationXavier Leroy2017-07-052-11/+26
| | | | This happens when the divisor of an unsigned int32 division is constant-propagated to 1.
* Adopted section names in AsmToJson.Bernhard Schommer2017-06-291-10/+23
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* Formatted json printing.Bernhard Schommer2017-06-282-315/+307
| | | | | | | | | Instead of just dumping the json output it is now a little bit formatted for better reading. Furthermore the AsmToJson function for the non powerpc targets now prints the json value "null" sucht that the resulting json file is valid json.
* Added pseudo instruction for inline asm.Bernhard Schommer2017-06-201-0/+15
| | | | | | The inline assembler instructions are numbered with consecutives id's per compilation unit. Bug 21689
* Print 64bit constants for rldimn and rldimi.Bernhard Schommer2017-05-051-2/+2
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* bug 20956, print correct error message depending on architectureMichael Schmidt2017-05-031-2/+8
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* More asserts.Bernhard Schommer2017-05-031-1/+1
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* Hybrid 64bit/32bit PowerPC portBernhard Schommer2017-05-0322-189/+2378
| | | | | | | | | | | | | This commit adds code generation for 64bit PowerPC architectures which execute 32bit applications. The main difference to the normal 32bit PowerPC port is that it uses the available 64bit instructions instead of using the runtime library functions. However pointers are still 32bit and the 32bit calling convention is used. In order to use this port the target architecture must be either in Server execution mode or if in Embedded execution mode the high order 32 bits of GPRs must be implemented in 32-bit mode. Furthermore the operating system must preserve the high order 32 bits of GPRs.
* RISC-V port and assorted changesXavier Leroy2017-04-282-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commits adds code generation for the RISC-V architecture, both in 32- and 64-bit modes. The generated code was lightly tested using the simulator and cross-binutils from https://riscv.org/software-tools/ This port required the following additional changes: - Integers: More properties about shrx - SelectOp: now provides smart constructors for mulhs and mulhu - SelectDiv, 32-bit integer division and modulus: implement constant propagation, use the new smart constructors mulhs and mulhu. - Runtime library: if no asm implementation is provided, run the reference C implementation through CompCert. Since CompCert rejects the definitions of names of special functions such as __i64_shl, the reference implementation now uses "i64_" names, e.g. "i64_shl", and a renaming "i64_ -> __i64_" is performed over the generated assembly file, before assembling and building the runtime library. - test/: add SIMU make variable to run tests through a simulator - test/regression/alignas.c: make sure _Alignas and _Alignof are not #define'd by C headers commit da14495c01cf4f66a928c2feff5c53f09bde837f Author: Xavier Leroy <xavier.leroy@inria.fr> Date: Thu Apr 13 17:36:10 2017 +0200 RISC-V port, continued Now working on Asmgen. commit 36f36eb3a5abfbb8805960443d087b6a83e86005 Author: Xavier Leroy <xavier.leroy@inria.fr> Date: Wed Apr 12 17:26:39 2017 +0200 RISC-V port, first steps This port is based on Prashanth Mundkur's experimental RV32 port and brings it up to date with CompCert, and adds 64-bit support (RV64). Work in progress.
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