diff options
| -rw-r--r-- | README.md | 22 | ||||
| -rw-r--r-- | scripts/vivado/synth_area_top.v | 20 |
2 files changed, 19 insertions, 23 deletions
@@ -533,17 +533,19 @@ place&route static timing analysis with `report_timing`. | Xilinx Virtex-7T | -3 | 2.4 ns (416 MHz) | The following table lists the resource utilization in area-optimized synthesis, -as reported by Vivado 2015.1 post optimization with `report_utilization`. The -"small" core is PicoRV32 configured down to a RV32E cpu, the "regular" core is -PicoRV32 with its default settings and the "large" core is PicoRV32 with -enabled PCPI, IRQ and MUL features. +as reported by Vivado 2015.1 post optimization with `report_utilization`. + +PicoRV32 "small" is the core without counter instructions, with externally +latched `mem_rdata`, and without catching of misaligned memory access and +illegal instructions. + +PicoRV32 "regular" is simply the core with its default settings. + +And PicoRV32 "large" is with enabled PCPI, IRQ and MUL features. | Core Variant | Slice LUTs | LUTs as Memory | |:------------------ | ----------:| --------------:| -| PicoRV32 "small" | 855 | 48 | -| PicoRV32 "regular" | 996 | 48 | -| PicoRV32 "large" | 1814 | 88 | - -*Note: Most of the size reduction in the "small" core comes from eliminating -the counter instructions, not from reducing the size of the register file.* +| PicoRV32 "small" | 828 | 48 | +| PicoRV32 "regular" | 968 | 48 | +| PicoRV32 "large" | 1742 | 88 | diff --git a/scripts/vivado/synth_area_top.v b/scripts/vivado/synth_area_top.v index 559ae6e..4d2b573 100644 --- a/scripts/vivado/synth_area_top.v +++ b/scripts/vivado/synth_area_top.v @@ -1,7 +1,6 @@ module top_small ( input clk, resetn, - output trap, output mem_valid, output mem_instr, @@ -14,13 +13,12 @@ module top_small ( ); picorv32 #( .ENABLE_COUNTERS(0), - .ENABLE_REGS_16_31(0), - .ENABLE_REGS_DUALPORT(1), - .LATCHED_MEM_RDATA(1) + .LATCHED_MEM_RDATA(1), + .CATCH_MISALIGN(0), + .CATCH_ILLINSN(0) ) picorv32 ( .clk (clk ), .resetn (resetn ), - .trap (trap ), .mem_valid(mem_valid), .mem_instr(mem_instr), .mem_ready(mem_ready), @@ -91,13 +89,11 @@ module top_large ( output [ 3:0] mem_la_wstrb, // Pico Co-Processor Interface (PCPI) - output pcpi_insn_valid, + output pcpi_valid, output [31:0] pcpi_insn, - output pcpi_rs1_valid, output [31:0] pcpi_rs1, - output pcpi_rs2_valid, output [31:0] pcpi_rs2, - input pcpi_rd_valid, + input pcpi_wr, input [31:0] pcpi_rd, input pcpi_wait, input pcpi_ready, @@ -126,13 +122,11 @@ module top_large ( .mem_la_addr (mem_la_addr ), .mem_la_wdata (mem_la_wdata ), .mem_la_wstrb (mem_la_wstrb ), - .pcpi_insn_valid(pcpi_insn_valid), + .pcpi_valid (pcpi_valid ), .pcpi_insn (pcpi_insn ), - .pcpi_rs1_valid (pcpi_rs1_valid ), .pcpi_rs1 (pcpi_rs1 ), - .pcpi_rs2_valid (pcpi_rs2_valid ), .pcpi_rs2 (pcpi_rs2 ), - .pcpi_rd_valid (pcpi_rd_valid ), + .pcpi_wr (pcpi_wr ), .pcpi_rd (pcpi_rd ), .pcpi_wait (pcpi_wait ), .pcpi_ready (pcpi_ready ), |