diff options
Diffstat (limited to 'picosoc')
| -rw-r--r-- | picosoc/README.md | 2 | ||||
| -rw-r--r-- | picosoc/hx8kdemo.core | 35 | ||||
| -rw-r--r-- | picosoc/picosoc.core | 23 | ||||
| -rw-r--r-- | picosoc/picosoc.v | 2 | ||||
| -rw-r--r-- | picosoc/spiflash.core | 24 | ||||
| -rw-r--r-- | picosoc/spiflash.v | 5 | ||||
| -rw-r--r-- | picosoc/spiflash_tb.v | 12 |
7 files changed, 95 insertions, 8 deletions
diff --git a/picosoc/README.md b/picosoc/README.md index 91ea391..dcb45ba 100644 --- a/picosoc/README.md +++ b/picosoc/README.md @@ -53,7 +53,7 @@ physical SRAM will read from the corresponding addresses in serial flash. Reading from the UART Send/Recv Data Register will return the last received byte, or -1 (all 32 bits set) when the receive buffer is empty. -The UART Clock Divider Register must be set to the system clock freuqency +The UART Clock Divider Register must be set to the system clock frequency divided by the baud rate. The example design (hx8kdemo.v) has the 8 LEDs on the iCE40-HX8K Breakout Board diff --git a/picosoc/hx8kdemo.core b/picosoc/hx8kdemo.core new file mode 100644 index 0000000..97a1989 --- /dev/null +++ b/picosoc/hx8kdemo.core @@ -0,0 +1,35 @@ +CAPI=2: + +name : ::hx8kdemo:0 + +filesets: + hx8kdemo: + files: [hx8kdemo.v] + file_type : verilogSource + depend : [picosoc] + hx8ksim: + files: + - hx8kdemo_tb.v + file_type : verilogSource + depend : [spiflash, "yosys:techlibs:ice40"] + + constraints: + files: [hx8kdemo.pcf] + file_type : PCF + +targets: + synth: + default_tool : icestorm + filesets : [constraints, hx8kdemo] + tools: + icestorm: + arachne_pnr_options : [-d, 8k] + toplevel : [hx8kdemo] + sim: + default_tool : icarus + filesets : [hx8kdemo, hx8ksim] + tools: + xsim: + xelab_options : [--timescale, 1ns/1ps] + + toplevel : [testbench] diff --git a/picosoc/picosoc.core b/picosoc/picosoc.core new file mode 100644 index 0000000..a6eae08 --- /dev/null +++ b/picosoc/picosoc.core @@ -0,0 +1,23 @@ +CAPI=2: + +name : ::picosoc:0 + +filesets: + picosoc: + files: + - simpleuart.v + - spimemio.v + - picosoc.v + file_type : verilogSource + depend : [picorv32] + +targets: + default: + filesets : [picosoc] + parameters : [PICORV32_REGS] + +parameters: + PICORV32_REGS: + datatype : str + default : picosoc_regs + paramtype : vlogdefine diff --git a/picosoc/picosoc.v b/picosoc/picosoc.v index 0f82df5..6298a8e 100644 --- a/picosoc/picosoc.v +++ b/picosoc/picosoc.v @@ -17,11 +17,13 @@ * */ +`ifndef PICORV32_REGS `ifdef PICORV32_V `error "picosoc.v must be read before picorv32.v!" `endif `define PICORV32_REGS picosoc_regs +`endif module picosoc ( input clk, diff --git a/picosoc/spiflash.core b/picosoc/spiflash.core new file mode 100644 index 0000000..1b7d153 --- /dev/null +++ b/picosoc/spiflash.core @@ -0,0 +1,24 @@ +CAPI=2: + +name : ::spiflash:0 + +filesets: + model: + files : [spiflash.v] + file_type : verilogSource + tb: + files : [spiflash_tb.v] + file_type : verilogSource + +targets: + default: + default_tool : icarus + filesets : [model, "is_toplevel? (tb)"] + parameters : [firmware] + toplevel : [testbench] + +parameters : + firmware: + datatype : file + description : Initial SPI Flash contents (in verilog hex format) + paramtype : plusarg diff --git a/picosoc/spiflash.v b/picosoc/spiflash.v index 63d21dc..18b918b 100644 --- a/picosoc/spiflash.v +++ b/picosoc/spiflash.v @@ -98,8 +98,11 @@ module spiflash ( // 16 MB (128Mb) Flash reg [7:0] memory [0:16*1024*1024-1]; + reg [1023:0] firmware_file; initial begin - $readmemh("firmware.hex", memory); + if (!$value$plusargs("firmware=%s", firmware_file)) + firmware_file = "firmware.hex"; + $readmemh(firmware_file, memory); end task spi_action; diff --git a/picosoc/spiflash_tb.v b/picosoc/spiflash_tb.v index ce2e949..f300373 100644 --- a/picosoc/spiflash_tb.v +++ b/picosoc/spiflash_tb.v @@ -53,8 +53,8 @@ module testbench; ); localparam [23:0] offset = 24'h100000; - localparam [31:0] word0 = 32'h 01300293; - localparam [31:0] word1 = 32'h 00502223; + localparam [31:0] word0 = 32'h 00000093; + localparam [31:0] word1 = 32'h 00000193; reg [7:0] rdata; integer errcount = 0; @@ -291,7 +291,7 @@ module testbench; xfer_qspi_wr(offset[15:8]); xfer_qspi_wr(offset[7:0]); xfer_qspi_wr(8'h a5); - xfer_dummy; + repeat (8) xfer_dummy; xfer_qspi_rd; expect(word0[7:0]); xfer_qspi_rd; expect(word0[15:8]); xfer_qspi_rd; expect(word0[23:16]); @@ -308,7 +308,7 @@ module testbench; xfer_qspi_wr(offset[15:8]); xfer_qspi_wr(offset[7:0]); xfer_qspi_wr(8'h ff); - xfer_dummy; + repeat (8) xfer_dummy; xfer_qspi_rd; expect(word0[7:0]); xfer_qspi_rd; expect(word0[15:8]); xfer_qspi_rd; expect(word0[23:16]); @@ -326,7 +326,7 @@ module testbench; xfer_qspi_ddr_wr(offset[15:8]); xfer_qspi_ddr_wr(offset[7:0]); xfer_qspi_ddr_wr(8'h a5); - xfer_dummy; + repeat (8) xfer_dummy; xfer_qspi_ddr_rd; expect(word0[7:0]); xfer_qspi_ddr_rd; expect(word0[15:8]); xfer_qspi_ddr_rd; expect(word0[23:16]); @@ -343,7 +343,7 @@ module testbench; xfer_qspi_ddr_wr(offset[15:8]); xfer_qspi_ddr_wr(offset[7:0]); xfer_qspi_ddr_wr(8'h ff); - xfer_dummy; + repeat (8) xfer_dummy; xfer_qspi_ddr_rd; expect(word0[7:0]); xfer_qspi_ddr_rd; expect(word0[15:8]); xfer_qspi_ddr_rd; expect(word0[23:16]); |