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-rw-r--r--scripts/cxxdemo/Makefile11
-rw-r--r--scripts/cxxdemo/testbench.v4
2 files changed, 9 insertions, 6 deletions
diff --git a/scripts/cxxdemo/Makefile b/scripts/cxxdemo/Makefile
index 444aa34..d811427 100644
--- a/scripts/cxxdemo/Makefile
+++ b/scripts/cxxdemo/Makefile
@@ -1,6 +1,7 @@
-CXX = riscv32-unknown-elf-g++
-CC = riscv32-unknown-elf-gcc
-AS = riscv32-unknown-elf-gcc
+RISCV_TOOLS_PREFIX = /opt/riscv32ic/bin/riscv32-unknown-elf-
+CXX = $(RISCV_TOOLS_PREFIX)g++
+CC = $(RISCV_TOOLS_PREFIX)gcc
+AS = $(RISCV_TOOLS_PREFIX)gcc
CXXFLAGS = -MD -Os -Wall -std=c++11
CCFLAGS = -MD -Os -Wall -std=c++11
LDFLAGS = -Wl,--gc-sections
@@ -14,8 +15,8 @@ testbench.exe: testbench.v ../../picorv32.v
chmod -x testbench.exe
firmware32.hex: firmware.elf start.elf hex8tohex32.py
- riscv32-unknown-elf-objcopy -O verilog start.elf start.tmp
- riscv32-unknown-elf-objcopy -O verilog firmware.elf firmware.tmp
+ $(RISCV_TOOLS_PREFIX)objcopy -O verilog start.elf start.tmp
+ $(RISCV_TOOLS_PREFIX)objcopy -O verilog firmware.elf firmware.tmp
cat start.tmp firmware.tmp > firmware.hex
python3 hex8tohex32.py firmware.hex > firmware32.hex
rm -f start.tmp firmware.tmp
diff --git a/scripts/cxxdemo/testbench.v b/scripts/cxxdemo/testbench.v
index 07cea2b..ac9af70 100644
--- a/scripts/cxxdemo/testbench.v
+++ b/scripts/cxxdemo/testbench.v
@@ -23,7 +23,9 @@ module testbench;
wire [3:0] mem_wstrb;
reg [31:0] mem_rdata;
- picorv32 uut (
+ picorv32 #(
+ .COMPRESSED_ISA(1)
+ ) uut (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),