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author | Yann Herklotz <ymh15@ic.ac.uk> | 2020-11-21 10:51:53 +0000 |
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committer | overleaf <overleaf@localhost> | 2020-11-21 10:58:40 +0000 |
commit | 94dbc2a5e70ffa2d6b4a464cb2880dd4affdccfe (patch) | |
tree | ba5a9682589bc6e44bd4b027572e65609e3602c6 | |
parent | 9817ee1243e45cbcd7869e8122ebd848b9984026 (diff) | |
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Update on Overleaf.
-rw-r--r-- | algorithm.tex | 2 |
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diff --git a/algorithm.tex b/algorithm.tex index e520c2c..3a8882c 100644 --- a/algorithm.tex +++ b/algorithm.tex @@ -15,7 +15,7 @@ We also considered using a language with built-in parallel constructs that map w \paragraph{Choice of target language} -Verilog~\cite{06_ieee_stand_veril_hardw_descr_languag} is an HDL that can be synthesised into logic cells which can be either placed onto a field-programmable gate array (FPGA) or turned into an application-specific integrated circuit (ASIC). Verilog was chosen as the output language for \vericert{} because it is one of the most popular HDLs and there already exist a few formal semantics for it that could be used as a target~\cite{loow19_verif_compil_verif_proces, meredith10_veril}. Bluespec, previously ruled out as a source language, is another possible target and there exists a formally verified translation to circuits using K\^{o}ika~\cite{bourgeat20_essen_blues}. %\JP{This needs an extra comment maybe?}\YH{Maybe about bluespec not being an ideal target language because it's quite high-level?} % but targeting this language would not be trivial as it is not meant to be targeted by an automatic tool, instead strives to a formally verified high-level hardware description language instead. +Verilog~\cite{06_ieee_stand_veril_hardw_descr_languag} is an HDL that can be synthesised into logic cells which can either be placed onto a field-programmable gate array (FPGA) or turned into an application-specific integrated circuit (ASIC). Verilog was chosen as the output language for \vericert{} because it is one of the most popular HDLs and there already exist a few formal semantics for it that could be used as a target~\cite{loow19_verif_compil_verif_proces, meredith10_veril}. Bluespec, previously ruled out as a source language, is another possible target and there exists a formally verified translation to circuits using K\^{o}ika~\cite{bourgeat20_essen_blues}. %\JP{This needs an extra comment maybe?}\YH{Maybe about bluespec not being an ideal target language because it's quite high-level?} % but targeting this language would not be trivial as it is not meant to be targeted by an automatic tool, instead strives to a formally verified high-level hardware description language instead. %\JW{Can we mention one or two alternatives that we considered? Bluespec or Chisel or one of Adam Chlipala's languages, perhaps?} |