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-rw-r--r-- | evaluation.tex | 15 | ||||
-rw-r--r-- | main.tex | 2 |
2 files changed, 1 insertions, 16 deletions
diff --git a/evaluation.tex b/evaluation.tex index dd206ec..9e000b0 100644 --- a/evaluation.tex +++ b/evaluation.tex @@ -16,21 +16,6 @@ Our evaluation is designed to answer the following three research questions. \paragraph{Experimental setup.} In order to generate a hardware implementation, the Verilog produced by the HLS tool-under-test must be synthesised to a netlist; the resultant netlist can then be placed-and-routed for a particular FPGA device. We use Intel Quartus~\cite{quartus} for both of these tasks, and we target an Arria 10 FPGA. -\begin{table*} - \begin{tabular}{lcccccccccccc} - \toprule - \textbf{Benchmark} & \multicolumn{2}{c}{\bf Cycles} & \multicolumn{2}{c}{\bf Frequency / MHz} & \multicolumn{2}{c}{\bf LUTs} & \multicolumn{2}{c}{\bf Registers} & \multicolumn{2}{c}{\bf Block RAMs} & \multicolumn{2}{c}{\bf DSPs}\\ - & L & V & L & V & L & V & L & V & L & V & L & V\\ - \midrule - adpcm & 30241 & 121386 & 90.05 & 66.3 & 7719 & 51626 & 12034 & 42688 & 7 & 0 & 0 & 48\\ - aes & 8489 & 41958 & 87.83 & 19.6 & 24413 & 104017 & 23796 & 94239 & 19 & 0 & 0 & 6\\ - gsm & 7190 & 21994 & 119.25 & 66.1 & 6638 & 45764 & 9201 & 33675 & 3 & 0 & 0 & 8 \\ - mips & 7754 & 18482 & 98.95 & 78.43 & 5049 & 10617 & 4185 & 7690 & 0 & 0 & 0 & 0\\ - \bottomrule - \end{tabular} - \caption{CHStone programs synthesised with \legup{} 5.1 (L) and with \vericert{} (V) \JW{I guess this table is for the chop?}}\label{tab:chstone} -\end{table*} - \subsection{RQ1: How fast is \vericert{}-generated hardware?} \begin{figure} @@ -54,7 +54,7 @@ \ANONYMOUStrue \newif\ifCOMMENTS -\COMMENTStrue +\COMMENTSfalse \newcommand{\Comment}[3]{\ifCOMMENTS\textcolor{#1}{{\bf [\![#2:} #3{\bf ]\!]}}\fi} \newcommand\JW[1]{\Comment{red!75!black}{JW}{#1}} \newcommand\YH[1]{\Comment{green!50!blue}{YH}{#1}} |