diff options
| -rw-r--r-- | algorithm.tex | 2 | ||||
| -rw-r--r-- | evaluation.tex | 51 |
2 files changed, 41 insertions, 12 deletions
diff --git a/algorithm.tex b/algorithm.tex index f50a482..a2f8c8c 100644 --- a/algorithm.tex +++ b/algorithm.tex @@ -5,7 +5,7 @@ This section covers the main architecture of the HLS tool, and the way in which the back end was added to \compcert{}. This section will also cover an example of converting a simple C program into hardware, expressed in the Verilog language. %\JW{I've experimented with adding a few paragraph headings to the text below -- see what you think. The advantage of headings is that it can make the text easier to read quickly.}\YH{Yes I think it works well actually, makes the sections clearer.} -\paragraph{Choice of source language}\YH{Could combine this with ``Choice of implementation language'' maybe, as there is a bit of overlap.} +\paragraph{Choice of source language}\YH{Could combine this with ``Choice of implementation language'' maybe, as there is a bit of overlap.} \JW{Although the answers to these questions happen to overlap, I think the questions are distinct and it is logical to ask them separately.} First of all, the choice of C for the input language of \vericert{} is because it is the most widely supported language for HLS, and most major HLS tools also use it as an input. As a lot of existing code is also written in C for HLS, supporting C as an input language compared to a custom domain-specific language means that \vericert{} is more practical. Another alternative was to support LLVM IR as an input language, however, to get a full work flow from a higher level language to hardware, a front end for that language to LLVM IR would also have to be verified. Finally, a language similar to Occam was also considered, as it has inherent parallel constructs, however, this would not qualify as being high-level synthesis due to the manual parallelism that would have to be performed. %\JW{Can we mention one or two alternatives that we considered?} \paragraph{Choice of target language} diff --git a/evaluation.tex b/evaluation.tex index 2a444df..13ab4b4 100644 --- a/evaluation.tex +++ b/evaluation.tex @@ -49,25 +49,54 @@ Our evaluation is designed to answer the following three research questions. \JW ymode=log, height=80mm, width=80mm, - xlabel={LegUp (ms)}, - ylabel={\vericert{} (ms)}, + xlabel={\legup{} cycle count}, + ylabel={\vericert{} cycle count}, + xmin=1000, + xmax=10000000, + ymax=10000000, + ymin=1000, + %log ticks with fixed point, + ] + +\addplot[draw=none, mark=*, draw opacity=0, fill opacity=0.3] + table [x=legupcycles, y=vericertcycles, col sep=comma] + {results/poly.csv}; + +\addplot[dotted, domain=1000:10000000]{x}; +%\addplot[dashed, domain=10:10000]{9.02*x}; + +\end{axis} +\end{tikzpicture} +\caption{A comparison of the cycle count of hardware designs generated by \vericert{} and by \legup{}.} +\label{fig:comparison_cycles} +\end{figure} + +\begin{figure} +\begin{tikzpicture} +\begin{axis}[ + xmode=log, + ymode=log, + height=80mm, + width=80mm, + xlabel={\legup{} execution time (ms)}, + ylabel={\vericert{} execution time (ms)}, xmin=10, - xmax=10000, + xmax=100000, ymax=100000, ymin=10, - log ticks with fixed point, + %log ticks with fixed point, ] \addplot[draw=none, mark=*, draw opacity=0, fill opacity=0.3] table [x expr={\thisrow{legupcycles}/\thisrow{legupfreqMHz}}, y expr={\thisrow{vericertcycles}/\thisrow{vericertfreqMHz}}, col sep=comma] {results/poly.csv}; -\addplot[dotted, domain=10:10000]{x}; -\addplot[dashed, domain=10:10000]{9.02*x}; +\addplot[dotted, domain=10:100000]{x}; +%\addplot[dashed, domain=10:10000]{9.02*x}; \end{axis} \end{tikzpicture} -\caption{A comparison of the execution time of hardware designs generated by \vericert{} and by LegUp. The diagonal is at $y=9x$.} +\caption{A comparison of the execution time of hardware designs generated by \vericert{} and by \legup{}.} \label{fig:comparison_time} \end{figure} @@ -82,8 +111,8 @@ The difference in cycle counts shows the degree of parallelism that \legup{}'s \begin{axis}[ height=80mm, width=80mm, - xlabel={LegUp (\%)}, - ylabel={\vericert{} (\%)}, + xlabel={\legup{} resource utilisation (\%)}, + ylabel={\vericert{} resource utilisation (\%)}, xmin=0, ymin=0, xmax=1, ymax=30, ] @@ -109,8 +138,8 @@ Figure~\ref{fig:comparison_area} compares the size of the hardware designs gener \begin{axis}[ height=80mm, width=80mm, - xlabel={LegUp (s)}, - ylabel={\vericert{} (s)}, + xlabel={\legup{} compilation time (s)}, + ylabel={\vericert{} compilation time (s)}, yticklabel style={ /pgf/number format/fixed, /pgf/number format/precision=2}, |