1 files changed, 68 insertions, 0 deletions
diff --git a/pipeline.sv b/pipeline.sv
new file mode 100644
index 0000000..7c7c27c
--- /dev/null
+++ b/pipeline.sv
@@ -0,0 +1,68 @@
+module ram(clk, addr, idata, wr_en, odata);
+   input logic         clk;
+   input logic [31:0]  addr;
+   input logic [31:0]  idata;
+   input logic         wr_en;
+
+   output logic [31:0] odata;
+
+   logic [31:0]        ram [9:0];
+
+   always @(posedge clk) begin
+      if (wr_en) begin
+         ram[addr] <= idata;
+      end
+   end
+
+   assign odata = ram[addr];
+endmodule
+
+module pipeline(valid, clk, x1, x6, fin, val);
+   input logic         start;
+   input logic         clk;
+   input logic [31:0]  x1;
+   input logic [31:0]  x6;
+
+   output logic        fin;
+   output logic [31:0] val;
+
+   logic [31:0]        x18, x16, x8, x12, x13, x7, x11;
+
+   logic [1:0]         state;
+
+   logic [31:0]        ram1 [9:0];
+   logic [31:0]        ram2 [9:0];
+   logic [31:0]        ram3 [9:0];
+
+   parameter           IDLE   = 0;
+   parameter           STATE1 = 1;
+   parameter           STATE2 = 2;
+
+   initial begin
+      state = IDLE;
+   end
+
+   always @(posedge clk) begin
+      case(state)
+        IDLE: begin
+           if (start) state <= STATE1;
+        end
+        STATE1: state <= STATE2;
+        STATE2: state <= STATE1;
+      endcase
+   end
+
+   always @(posedge clk) begin
+      if (state == STATE1) begin
+         x18 <= x6 - 1;
+         x12 <= ram2[x6];
+         x13 <= ram3[x6];
+      end
+   end
+
+   always @(posedge clk) begin
+      if (state == STATE2) begin
+         x16 <= ram1[x18];
+      end
+   end
+endmodule