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author | Yann Herklotz <git@yannherklotz.com> | 2020-06-12 11:37:00 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-06-12 11:37:00 +0100 |
commit | 1ceb1a28f0e08406862f03863c5d00639ada147d (patch) | |
tree | 6d1125b9967b7bbf151d0f942e41ecdc3ff761f4 | |
parent | 5355eb2e4346043d8a4ea4cb574a5b47b5a3a1f3 (diff) | |
download | vericert-kvx-1ceb1a28f0e08406862f03863c5d00639ada147d.tar.gz vericert-kvx-1ceb1a28f0e08406862f03863c5d00639ada147d.zip |
Fix top level invocation to translate through HTL
-rw-r--r-- | src/Compiler.v | 9 | ||||
-rw-r--r-- | src/Simulator.v | 3 |
2 files changed, 8 insertions, 4 deletions
diff --git a/src/Compiler.v b/src/Compiler.v index e998521..98ef429 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -74,9 +74,12 @@ Proof. intros. destruct x; simpl. rewrite print_identity. auto. auto. Qed. -Definition transf_backend (r : RTL.program) : res Verilog.module := +Definition transf_backend (r : RTL.program) : res Verilog.program := OK r - @@@ Veriloggen.transf_program. + @@@ Inlining.transf_program + @@ print (print_RTL 1) + @@@ HTLgen.transl_program + @@ Veriloggen.transl_program. Definition transf_frontend (p: Csyntax.program) : res RTL.program := OK p @@ -88,7 +91,7 @@ Definition transf_frontend (p: Csyntax.program) : res RTL.program := @@@ RTLgen.transl_program @@ print (print_RTL 0). -Definition transf_hls (p : Csyntax.program) : res Verilog.module := +Definition transf_hls (p : Csyntax.program) : res Verilog.program := OK p @@@ transf_frontend @@@ transf_backend. diff --git a/src/Simulator.v b/src/Simulator.v index 930971b..83d3e96 100644 --- a/src/Simulator.v +++ b/src/Simulator.v @@ -16,7 +16,7 @@ * along with this program. If not, see <https://www.gnu.org/licenses/>. *) -From Coq Require Import FSets.FMapPositive. +(*From Coq Require Import FSets.FMapPositive. From compcert Require Import Errors. @@ -33,3 +33,4 @@ Definition simulate (n : nat) (m : Verilog.module) : res (Value.value * list (po end. Local Close Scope error_monad_scope. +*) |