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author | Yann Herklotz <git@yannherklotz.com> | 2020-04-17 14:55:57 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2020-04-17 14:55:57 +0100 |
commit | ae30c51b001b43e292c1e2b48799bf197d7b89ec (patch) | |
tree | 2178b075fb0fee981eda853b631ac191a89a7280 | |
parent | 5ea04d4bbec608cfe54f8722774ed581c9834c2a (diff) | |
download | vericert-kvx-ae30c51b001b43e292c1e2b48799bf197d7b89ec.tar.gz vericert-kvx-ae30c51b001b43e292c1e2b48799bf197d7b89ec.zip |
Extract simulator
-rw-r--r-- | src/Compiler.v | 4 | ||||
-rw-r--r-- | src/extraction/Extraction.v | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/Compiler.v b/src/Compiler.v index 5b4ef0a..697732d 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -1,4 +1,4 @@ -(* +(* -*- mode: coq -*- * CoqUp: Verified high-level synthesis. * Copyright (C) 2019-2020 Yann Herklotz <yann@yannherklotz.com> * @@ -74,7 +74,7 @@ Proof. intros. destruct x; simpl. rewrite print_identity. auto. auto. Qed. -Definition transf_backend (r : RTL.program) : res Verilog.module := +Definition transf_backend (r : RTL.program) : res Verilog.module := OK r @@@ Veriloggen.transf_program. diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index ff0b8ba..319e2eb 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -1,4 +1,4 @@ -(* +(* -*- mode: coq -*- * CoqUp: Verified high-level synthesis. * Copyright (C) 2019-2020 Yann Herklotz <yann@yannherklotz.com> * @@ -16,7 +16,7 @@ * along with this program. If not, see <https://www.gnu.org/licenses/>. *) -From coqup Require Verilog Compiler. +From coqup Require Verilog Value Compiler Simulator. From Coq Require DecidableClass. @@ -166,7 +166,7 @@ Set Extraction AccessOpaque. Cd "src/extraction". Separate Extraction - Verilog.module Verilog.valueToZ coqup.Compiler.transf_hls + Verilog.module Value.uvalueToZ coqup.Compiler.transf_hls Simulator.simulate Compiler.transf_c_program Compiler.transf_cminor_program Cexec.do_initial_state Cexec.do_step Cexec.at_final_state |