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author | James Pollard <james@pollard.dev> | 2020-06-29 21:30:44 +0100 |
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committer | James Pollard <james@pollard.dev> | 2020-06-29 21:30:44 +0100 |
commit | 1bfb8971328f63f5ae963eef45d7f3d4b9971a2a (patch) | |
tree | 7951f3bb3726a092f6af88d58e9494b24c471edc | |
parent | 1e0d5047d2272fdeb06391d1c5fa4e0472be2365 (diff) | |
parent | 7e59d2723fb9c5b4631f5eac1e99ae8956871a7f (diff) | |
download | vericert-kvx-1bfb8971328f63f5ae963eef45d7f3d4b9971a2a.tar.gz vericert-kvx-1bfb8971328f63f5ae963eef45d7f3d4b9971a2a.zip |
Merge branch 'develop' into arrays-proof
-rw-r--r-- | Makefile | 1 | ||||
-rw-r--r-- | src/translation/HTLgen.v | 10 | ||||
-rw-r--r-- | src/translation/Veriloggenproof.v | 6 | ||||
-rw-r--r-- | src/verilog/Value.v | 22 |
4 files changed, 31 insertions, 8 deletions
@@ -67,3 +67,4 @@ clean:: Makefile.coq clean:: rm -f */*.v.d */*.glob */*.vo */*~ *~ + rm -f src/extraction/*.ml src/extraction/*.mli diff --git a/src/translation/HTLgen.v b/src/translation/HTLgen.v index 59fb70a..b32ed9d 100644 --- a/src/translation/HTLgen.v +++ b/src/translation/HTLgen.v @@ -294,24 +294,24 @@ Definition translate_eff_addressing (a: Op.addressing) (args: list reg) : mon ex | Op.Aindexed off, r1::nil => if (check_address_parameter_signed off) then ret (boplitz Vadd r1 off) - else error (Errors.msg "Veriloggen: translate_eff_addressing address misaligned") + else error (Errors.msg "Veriloggen: translate_eff_addressing (Aindexed): address misaligned") | Op.Ascaled scale offset, r1::nil => if (check_address_parameter_signed scale) && (check_address_parameter_signed offset) then ret (Vbinop Vadd (boplitz Vmul r1 scale) (Vlit (ZToValue 32 offset))) - else error (Errors.msg "Veriloggen: translate_eff_addressing address misaligned") + else error (Errors.msg "Veriloggen: translate_eff_addressing (Ascaled): address misaligned") | Op.Aindexed2 offset, r1::r2::nil => if (check_address_parameter_signed offset) then ret (Vbinop Vadd (Vvar r1) (boplitz Vadd r2 offset)) - else error (Errors.msg "Veriloggen: translate_eff_addressing address misaligned") + else error (Errors.msg "Veriloggen: translate_eff_addressing (Aindexed2): address misaligned") | Op.Aindexed2scaled scale offset, r1::r2::nil => (* Typical for dynamic array addressing *) if (check_address_parameter_signed scale) && (check_address_parameter_signed offset) then ret (Vbinop Vadd (boplitz Vadd r1 offset) (boplitz Vmul r2 scale)) - else error (Errors.msg "Veriloggen: translate_eff_addressing address misaligned") + else error (Errors.msg "Veriloggen: translate_eff_addressing (Aindexed2scaled): address misaligned") | Op.Ainstack a, nil => (* We need to be sure that the base address is aligned *) let a := Integers.Ptrofs.unsigned a in if (check_address_parameter_unsigned a) then ret (Vlit (ZToValue 32 a)) - else error (Errors.msg "Veriloggen: translate_eff_addressing address misaligned") + else error (Errors.msg "Veriloggen: translate_eff_addressing (Ainstack): address misaligned") | _, _ => error (Errors.msg "Veriloggen: translate_eff_addressing unsuported addressing") end. diff --git a/src/translation/Veriloggenproof.v b/src/translation/Veriloggenproof.v index db96949..ca4ecab 100644 --- a/src/translation/Veriloggenproof.v +++ b/src/translation/Veriloggenproof.v @@ -69,12 +69,14 @@ Section CORRECTNESS. match_states S1 R1 -> exists R2, Smallstep.plus step tge R1 t R2 /\ match_states S2 R2. Proof. - induction 1; intros R1 MSTATE; inv MSTATE; econstructor; split. +(* induction 1; intros R1 MSTATE; inv MSTATE; econstructor; split. - apply Smallstep.plus_one. econstructor. eassumption. trivial. - * econstructor. econstructor. + * econstructor. econstructor.*) + Admitted. Theorem transf_program_correct: forward_simulation (HTL.semantics prog) (Verilog.semantics tprog). + Admitted. End CORRECTNESS. diff --git a/src/verilog/Value.v b/src/verilog/Value.v index e7b2362..c380ca7 100644 --- a/src/verilog/Value.v +++ b/src/verilog/Value.v @@ -108,6 +108,12 @@ Definition boolToValue (sz : nat) (b : bool) : value := Definition unify_word (sz1 sz2 : nat) (w1 : word sz2): sz1 = sz2 -> word sz1. intros; subst; assumption. Defined. +Lemma unify_word_unfold : + forall sz w, + unify_word sz sz w eq_refl = w. +Proof. + intros. unfold unify_word. Admitted. + Definition value_eq_size: forall v1 v2 : value, { vsize v1 = vsize v2 } + { True }. Proof. @@ -382,7 +388,21 @@ Qed. Lemma boolToValue_ValueToBool : forall b, valueToBool (boolToValue 32 b) = b. -Proof. destruct b; unfold valueToBool, boolToValue; simpl; trivial. Qed. +Proof. destruct b; auto. Qed. + +Lemma intToValue_eq_size : + forall n1 n2, + vsize (intToValue n1) = vsize (intToValue n2). +Proof. auto. Qed. + +Local Open Scope Z. + +Lemma zadd_vplus : + forall z1 z2, + valueToZ (vplus (ZToValue 32 z1) (ZToValue 32 z2) eq_refl) = z1 + z2. +Proof. + intros. unfold valueToZ, ZToValue. simpl. + Admitted. (*Lemma ZToValue_valueToNat : forall x sz, |