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| author | Nadesh Ramanathan <nadeshramanathan88@gmail.com> | 2020-07-07 15:32:13 +0100 |
|---|---|---|
| committer | Nadesh Ramanathan <nadeshramanathan88@gmail.com> | 2020-07-07 15:32:13 +0100 |
| commit | b141f1e5b58aaabd091f30d2371e43712fbaef38 (patch) | |
| tree | 7b036cbf26832c25d12e4d60930756bbec666cf5 | |
| parent | c0be24c8e577d54c11f8cf06512a14a7583a9bb1 (diff) | |
| download | vericert-kvx-b141f1e5b58aaabd091f30d2371e43712fbaef38.tar.gz vericert-kvx-b141f1e5b58aaabd091f30d2371e43712fbaef38.zip | |
remove const prop
| -rw-r--r-- | src/Compiler.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Compiler.v b/src/Compiler.v index 513b5fa..546ba87 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -80,7 +80,7 @@ Definition transf_backend (r : RTL.program) : res Verilog.program := @@ Tailcall.transf_program @@@ Inlining.transf_program @@ Renumber.transf_program - @@ Constprop.transf_program + (* @@ Constprop.transf_program *) @@ Renumber.transf_program @@@ CSE.transf_program @@@ Deadcode.transf_program |