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| author | Yann Herklotz <git@yannherklotz.com> | 2020-09-03 09:02:52 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-09-03 09:02:52 +0100 |
| commit | e7cafecf3f8c43ed3302f09e000d4f8775356876 (patch) | |
| tree | 3f252b5ad64e441a9c21fae213546c8a482ada4e | |
| parent | 0caef68781a0e33368d2874286f72be17d6d3263 (diff) | |
| download | vericert-kvx-e7cafecf3f8c43ed3302f09e000d4f8775356876.tar.gz vericert-kvx-e7cafecf3f8c43ed3302f09e000d4f8775356876.zip | |
Add fixes to run scheduling on compilation
| -rw-r--r-- | driver/VericertDriver.ml | 4 | ||||
| -rw-r--r-- | src/Compiler.v | 15 | ||||
| -rw-r--r-- | src/extraction/Extraction.v | 1 |
3 files changed, 17 insertions, 3 deletions
diff --git a/driver/VericertDriver.ml b/driver/VericertDriver.ml index f500499..2b8d45f 100644 --- a/driver/VericertDriver.ml +++ b/driver/VericertDriver.ml @@ -91,14 +91,14 @@ let compile_c_file sourcename ifile ofile = close_out oc end else begin let verilog = - match Vericert.Compiler0.transf_hls csyntax with + match Vericert.Compiler0.transf_hls_temp csyntax with | Vericert.Errors.OK v -> v | Vericert.Errors.Error msg -> let loc = file_loc sourcename in fatal_error loc "%a" print_error msg in let oc = open_out ofile in - Vericert.PrintVerilog.print_program !option_debug_hls oc verilog; + Vericert.PrintRTLBlock.print_program oc verilog; close_out oc end diff --git a/src/Compiler.v b/src/Compiler.v index 6efd7a2..7a99bdb 100644 --- a/src/Compiler.v +++ b/src/Compiler.v @@ -51,7 +51,9 @@ From vericert Require Verilog Veriloggen Veriloggenproof - HTLgen. + HTLgen + RTLBlock + RTLBlockgen. From compcert Require Import Smallstep. @@ -99,6 +101,17 @@ Definition transf_hls (p : Csyntax.program) : res Verilog.program := @@ print (print_RTL 0) @@@ transf_backend. +Definition transf_hls_temp (p : Csyntax.program) : res RTLBlock.program := + OK p + @@@ SimplExpr.transl_program + @@@ SimplLocals.transf_program + @@@ Cshmgen.transl_program + @@@ Cminorgen.transl_program + @@@ Selection.sel_program + @@@ RTLgen.transl_program + @@ print (print_RTL 0) + @@@ RTLBlockgen.transl_program. + Local Open Scope linking_scope. Definition CompCert's_passes := diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index 9755125..6fc8545 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -175,6 +175,7 @@ Set Extraction AccessOpaque. Cd "src/extraction". Separate Extraction Verilog.module Value.uvalueToZ vericert.Compiler.transf_hls + vericert.Compiler.transf_hls_temp RTLBlockgen.transl_program RTLBlock.successors_instr Compiler.transf_c_program Compiler.transf_cminor_program |