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| author | Nadesh Ramanathan <nadeshramanathan88@gmail.com> | 2020-07-07 15:33:32 +0100 |
|---|---|---|
| committer | Nadesh Ramanathan <nadeshramanathan88@gmail.com> | 2020-07-07 15:33:32 +0100 |
| commit | 5ca10a134176352b25a0b434d5508852c7314670 (patch) | |
| tree | cb24d9e17782c3ad08079b9090463008e70cb019 /src/extraction/Extraction.v | |
| parent | 65ac86da554770ba0e3a24d187037c6a72a8725b (diff) | |
| parent | e0fe2958baaa0c61159b2a0e330c323f9f2f646c (diff) | |
| download | vericert-kvx-5ca10a134176352b25a0b434d5508852c7314670.tar.gz vericert-kvx-5ca10a134176352b25a0b434d5508852c7314670.zip | |
Merge branch 'dev-nadesh-proven' of https://github.com/ymherklotz/coqup into dev-nadesh-proven
Diffstat (limited to 'src/extraction/Extraction.v')
| -rw-r--r-- | src/extraction/Extraction.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index df21dc4..5d10cd7 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -16,7 +16,7 @@ * along with this program. If not, see <https://www.gnu.org/licenses/>. *) -From coqup Require Verilog Value Compiler. +From coqup Require Verilog ValueInt Compiler. From Coq Require DecidableClass. @@ -167,7 +167,7 @@ Set Extraction AccessOpaque. Cd "src/extraction". Separate Extraction - Verilog.module Value.uvalueToZ coqup.Compiler.transf_hls + Verilog.module ValueInt.uvalueToZ coqup.Compiler.transf_hls Compiler.transf_c_program Compiler.transf_cminor_program Cexec.do_initial_state Cexec.do_step Cexec.at_final_state |