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| author | James Pollard <james@pollard.dev> | 2020-06-12 17:48:51 +0100 |
|---|---|---|
| committer | James Pollard <james@pollard.dev> | 2020-06-12 17:48:51 +0100 |
| commit | f7795011ea9ac0d34ee565d3832f15b649bf1827 (patch) | |
| tree | fd731b58626c8665032afd62068ece8cedc76eb0 /src/extraction/Extraction.v | |
| parent | 9acb804500b590edbff66cd802216f58dde169cd (diff) | |
| parent | 86f42b92d87020875e2a7ef4ba40de12d261685f (diff) | |
| download | vericert-kvx-f7795011ea9ac0d34ee565d3832f15b649bf1827.tar.gz vericert-kvx-f7795011ea9ac0d34ee565d3832f15b649bf1827.zip | |
Merge branch 'master' into arrays-proof
Diffstat (limited to 'src/extraction/Extraction.v')
| -rw-r--r-- | src/extraction/Extraction.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/extraction/Extraction.v b/src/extraction/Extraction.v index 0028fcb..ba87af6 100644 --- a/src/extraction/Extraction.v +++ b/src/extraction/Extraction.v @@ -16,7 +16,7 @@ * along with this program. If not, see <https://www.gnu.org/licenses/>. *) -From coqup Require Verilog Value Compiler Simulator. +From coqup Require Verilog Value Compiler. From Coq Require DecidableClass. @@ -166,7 +166,7 @@ Set Extraction AccessOpaque. Cd "src/extraction". Separate Extraction - Verilog.module Value.uvalueToZ coqup.Compiler.transf_hls Simulator.simulate + Verilog.module Value.uvalueToZ coqup.Compiler.transf_hls Compiler.transf_c_program Compiler.transf_cminor_program Cexec.do_initial_state Cexec.do_step Cexec.at_final_state |