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| author | Yann Herklotz <git@yannherklotz.com> | 2020-06-28 23:48:06 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-06-28 23:48:06 +0100 |
| commit | 0c360ec297c42d73c1090958d061447c2bfbe31b (patch) | |
| tree | 8990070566dd45f5a8198e67b970fa7cab768ffe /src/translation/HTLgenproof.v | |
| parent | a83cd5feed50d90de67da4ec78e0281520dbdf1f (diff) | |
| download | vericert-kvx-0c360ec297c42d73c1090958d061447c2bfbe31b.tar.gz vericert-kvx-0c360ec297c42d73c1090958d061447c2bfbe31b.zip | |
Fix proof again with Verilog semantics changes
Diffstat (limited to 'src/translation/HTLgenproof.v')
| -rw-r--r-- | src/translation/HTLgenproof.v | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/translation/HTLgenproof.v b/src/translation/HTLgenproof.v index 753dccf..2f296f2 100644 --- a/src/translation/HTLgenproof.v +++ b/src/translation/HTLgenproof.v @@ -18,7 +18,7 @@ From compcert Require RTL Registers AST Integers. From compcert Require Import Globalenvs Memory. -From coqup Require Import Coquplib HTLgenspec HTLgen Value AssocMap Array IntegerExtra ZExtra. +From coqup Require Import Coquplib HTLgenspec HTLgen Value AssocMap Array IntegerExtra. From coqup Require HTL Verilog. Require Import Lia. @@ -427,6 +427,7 @@ Section CORRECTNESS. split. apply Smallstep.plus_one. eapply HTL.step_module; eauto. + apply assumption_32bit. (* processing of state *) econstructor. simplify. @@ -646,6 +647,7 @@ Section CORRECTNESS. eexists. split. eapply Smallstep.plus_one. eapply HTL.step_module; eauto. + apply assumption_32bit. econstructor. econstructor. econstructor. simplify. econstructor. econstructor. econstructor. simplify. eapply Verilog.erun_Vbinop with (EQ := ?[EQ1]). (* FIXME: These will be shelved and cause sadness. *) @@ -859,6 +861,7 @@ Section CORRECTNESS. eexists. split. eapply Smallstep.plus_one. eapply HTL.step_module; eauto. + apply assumption_32bit. econstructor. econstructor. econstructor. simplify. econstructor. econstructor. econstructor. simplify. eapply Verilog.erun_Vbinop with (EQ := ?[EQ3]). (* FIXME: These will be shelved and cause sadness. *) @@ -1037,6 +1040,7 @@ Section CORRECTNESS. eexists. split. eapply Smallstep.plus_one. eapply HTL.step_module; eauto. + apply assumption_32bit. econstructor. econstructor. econstructor. simplify. econstructor. econstructor. econstructor. econstructor. simplify. @@ -1201,6 +1205,7 @@ Section CORRECTNESS. eexists. split. eapply Smallstep.plus_one. eapply HTL.step_module; eauto. + apply assumption_32bit. econstructor. econstructor. econstructor. eapply Verilog.stmnt_runp_Vnonblock_arr. simplify. econstructor. @@ -1454,6 +1459,7 @@ Section CORRECTNESS. eexists. split. eapply Smallstep.plus_one. eapply HTL.step_module; eauto. + apply assumption_32bit. econstructor. econstructor. econstructor. eapply Verilog.stmnt_runp_Vnonblock_arr. simplify. econstructor. @@ -1672,6 +1678,7 @@ Section CORRECTNESS. eexists. split. eapply Smallstep.plus_one. eapply HTL.step_module; eauto. + apply assumption_32bit. econstructor. econstructor. econstructor. eapply Verilog.stmnt_runp_Vnonblock_arr. simplify. econstructor. econstructor. econstructor. econstructor. @@ -1856,6 +1863,7 @@ Section CORRECTNESS. - eexists. split. apply Smallstep.plus_one. eapply HTL.step_module; eauto. + apply assumption_32bit. eapply Verilog.stmnt_runp_Vnonblock_reg with (rhsval := if b then posToValue 32 ifso else posToValue 32 ifnot). @@ -1966,6 +1974,7 @@ Section CORRECTNESS. eapply Smallstep.plus_two. eapply HTL.step_module; eauto. + apply assumption_32bit. constructor. econstructor; simpl; trivial. econstructor; simpl; trivial. @@ -1998,6 +2007,7 @@ Section CORRECTNESS. - econstructor. split. eapply Smallstep.plus_two. eapply HTL.step_module; eauto. + apply assumption_32bit. constructor. econstructor; simpl; trivial. econstructor; simpl; trivial. |