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| author | Yann Herklotz <git@yannherklotz.com> | 2020-06-26 09:40:16 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-06-26 09:40:31 +0100 |
| commit | 50ec2fb12454c2bc1f902c955f0b81df71b58c39 (patch) | |
| tree | 8ffd09be682442cedddc6106c242962e614e236c /src/translation/Veriloggen.v | |
| parent | cf9949a5151aa9ed86554fb31c2a56fad0614a10 (diff) | |
| download | vericert-kvx-50ec2fb12454c2bc1f902c955f0b81df71b58c39.tar.gz vericert-kvx-50ec2fb12454c2bc1f902c955f0b81df71b58c39.zip | |
Fix Verilog semantics and fix order of always blocks
Diffstat (limited to 'src/translation/Veriloggen.v')
| -rw-r--r-- | src/translation/Veriloggen.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/translation/Veriloggen.v b/src/translation/Veriloggen.v index 2b9974b..b550ff9 100644 --- a/src/translation/Veriloggen.v +++ b/src/translation/Veriloggen.v @@ -43,10 +43,10 @@ Definition transl_module (m : HTL.module) : Verilog.module := let case_el_ctrl := transl_list (PTree.elements m.(mod_controllogic)) in let case_el_data := transl_list (PTree.elements m.(mod_datapath)) in let body := - Valways (Vposedge m.(mod_clk)) (Vcase (Vvar m.(mod_st)) case_el_data (Some Vskip)) - :: Valways (Vposedge m.(mod_clk)) (Vcond (Vbinop Veq (Vvar m.(mod_reset)) (ZToValue 1 1)) + Valways (Vposedge m.(mod_clk)) (Vcond (Vbinop Veq (Vvar m.(mod_reset)) (ZToValue 1 1)) (Vnonblock (Vvar m.(mod_st)) (posToValue 32 m.(mod_entrypoint))) (Vcase (Vvar m.(mod_st)) case_el_ctrl (Some Vskip))) + :: Valways (Vposedge m.(mod_clk)) (Vcase (Vvar m.(mod_st)) case_el_data (Some Vskip)) :: (arr_to_Vdeclarr (AssocMap.elements m.(mod_arrdecls)) ++ scl_to_Vdecl (AssocMap.elements m.(mod_scldecls))) in Verilog.mkmodule m.(mod_start) |