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| author | Yann Herklotz <git@yannherklotz.com> | 2020-07-05 02:28:30 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-07-05 02:28:30 +0100 |
| commit | 322f3a1c2d547490b0e92a8f1ef937e1d68c2a6b (patch) | |
| tree | 3fe37ad25f087acfaaf87b4f89b0e265b3e69217 /src/verilog/HTL.v | |
| parent | ad8947508dd08294b9a7e0ca7b12972ae147365c (diff) | |
| download | vericert-kvx-322f3a1c2d547490b0e92a8f1ef937e1d68c2a6b.tar.gz vericert-kvx-322f3a1c2d547490b0e92a8f1ef937e1d68c2a6b.zip | |
Finish most of Veriloggenproof
Diffstat (limited to 'src/verilog/HTL.v')
| -rw-r--r-- | src/verilog/HTL.v | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/verilog/HTL.v b/src/verilog/HTL.v index df88f98..a7a6ecc 100644 --- a/src/verilog/HTL.v +++ b/src/verilog/HTL.v @@ -103,6 +103,8 @@ Inductive step : genv -> state -> Events.trace -> state -> Prop := basr2 basa2 nasr2 nasa2 asr' asa' f stval pstval, + asr!(mod_reset m) = Some (ZToValue 0) -> + asr!(mod_finish m) = Some (ZToValue 0) -> asr!(m.(mod_st)) = Some ist -> valueToPos ist = st -> m.(mod_controllogic)!st = Some ctrl -> @@ -113,6 +115,8 @@ Inductive step : genv -> state -> Events.trace -> state -> Prop := ctrl (Verilog.mkassociations basr1 nasr1) (Verilog.mkassociations basa1 nasa1) -> + basr1!(m.(mod_st)) = Some ist -> + valueToPos ist = st -> Verilog.stmnt_runp f (Verilog.mkassociations basr1 nasr1) (Verilog.mkassociations basa1 nasa1) |