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| author | Yann Herklotz <git@yannherklotz.com> | 2020-07-06 14:09:54 +0100 |
|---|---|---|
| committer | Yann Herklotz <git@yannherklotz.com> | 2020-07-06 14:09:54 +0100 |
| commit | 78e549331ba3f136ebe94955f68767bd384df454 (patch) | |
| tree | e82c58fc59b6b4b1e9472cf26ce35ce0e6efdf14 /src/verilog/HTL.v | |
| parent | c76ac9be323e3513aa0db2721ecd0f6c3987aef0 (diff) | |
| download | vericert-kvx-78e549331ba3f136ebe94955f68767bd384df454.tar.gz vericert-kvx-78e549331ba3f136ebe94955f68767bd384df454.zip | |
HTLgenproof compiles again
- Commented out Iload, Istore proofs for now
Diffstat (limited to 'src/verilog/HTL.v')
| -rw-r--r-- | src/verilog/HTL.v | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/verilog/HTL.v b/src/verilog/HTL.v index 3ba5b59..b3d1442 100644 --- a/src/verilog/HTL.v +++ b/src/verilog/HTL.v @@ -141,8 +141,10 @@ Inductive step : genv -> state -> Events.trace -> state -> Prop := forall g m args res, step g (Callstate res m args) Events.E0 (State res m m.(mod_entrypoint) - (AssocMap.set (mod_st m) (posToValue m.(mod_entrypoint)) - (init_regs args m.(mod_params))) + (AssocMap.set (mod_reset m) (ZToValue 0) + (AssocMap.set (mod_finish m) (ZToValue 0) + (AssocMap.set (mod_st m) (posToValue m.(mod_entrypoint)) + (init_regs args m.(mod_params))))) (empty_stack m)) | step_return : forall g m asr asa i r sf pc mst, |