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| author | James Pollard <james@pollard.dev> | 2020-05-26 19:10:14 +0100 |
|---|---|---|
| committer | James Pollard <james@pollard.dev> | 2020-05-26 19:10:14 +0100 |
| commit | 45842fdccf3f2fae7a14508fa939ba2a1cf0d3ce (patch) | |
| tree | 3132d12f55df2ed8daf6d95f1a6ec980f7c8dad0 /src/verilog/Verilog.v | |
| parent | 1baa474a2312a930187cd2d071dc0651451327d1 (diff) | |
| download | vericert-kvx-45842fdccf3f2fae7a14508fa939ba2a1cf0d3ce.tar.gz vericert-kvx-45842fdccf3f2fae7a14508fa939ba2a1cf0d3ce.zip | |
(Tentatively) working stack array/memory support.
Diffstat (limited to 'src/verilog/Verilog.v')
| -rw-r--r-- | src/verilog/Verilog.v | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/verilog/Verilog.v b/src/verilog/Verilog.v index 4713c36..dfb6255 100644 --- a/src/verilog/Verilog.v +++ b/src/verilog/Verilog.v @@ -95,6 +95,7 @@ Inductive unop : Type := Inductive expr : Type := | Vlit : value -> expr | Vvar : reg -> expr +| Vvari : reg -> expr -> expr | Vinputvar : reg -> expr | Vbinop : binop -> expr -> expr -> expr | Vunop : unop -> expr -> expr @@ -136,6 +137,7 @@ done using combinational always block instead of continuous assignments. *) Inductive module_item : Type := | Vdecl : reg -> nat -> module_item +| Vdeclarr : reg -> nat -> nat -> module_item | Valways : edge -> stmnt -> module_item | Valways_ff : edge -> stmnt -> module_item | Valways_comb : edge -> stmnt -> module_item. @@ -280,6 +282,7 @@ Fixpoint expr_run (s : state) (e : expr) | Vvar r => match s with | State assoc _ _ _ => handle_def (ZToValue 32 0) assoc!r end + | Vvari _ _ => Error (msg "Verilog: variable indexing not modelled") | Vinputvar r => access_fext s r | Vbinop op l r => let lv := expr_run s l in @@ -383,6 +386,7 @@ Fixpoint mi_step (s : state) (m : list module_item) {struct m} : res state := | (Valways_ff _ st)::ls => run st ls | (Valways_comb _ st)::ls => run st ls | (Vdecl _ _)::ls => mi_step s ls + | (Vdeclarr _ _ _)::ls => mi_step s ls | nil => OK s end. |